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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429898acd69sm3276609f8f.24.2025.10.23.03.34.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 03:34:24 -0700 (PDT) Message-ID: Date: Thu, 23 Oct 2025 12:34:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Add assert to arm_to_core_mmu_idx() Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson References: <20251023101339.1983809-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251023101339.1983809-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/10/25 12:13, Peter Maydell wrote: > Before commit f76cee647c ("target/arm: Introduce mmu indexes for > GCS") it was impossible for arm_to_core_mmu_idx() to return an > invalid core MMU index, because NB_MMU_MODES was 16 and > ARM_MMU_IDX_COREIDX_MASK was 0xf. > > That commit raises ARM_MMU_IDX_COREIDX_MASK to 0x1f and NB_MMU_MODES > to 22, so it's now possible for a bogus Arm mmu index to result in an > out of range core mmu index (which can then get used as an array > index in the CPUTLB struct arrays). Coverity complains that this > might result in an out-of-bounds access. > > The out-of-bounds access can't happen because we construct all the > ARMMMUIdx values we will use for TLBs to have valid core MMU indexes > in the COREIDX field. But we can add an assert() so that if we ever > do end up operating on a corrupted or wrong ARMMMUIdx value we get an > assert rather than silently indexing off the end of an array. This > should also make Coverity happier. > > Coverity: CID 1641404 > Signed-off-by: Peter Maydell > --- > target/arm/internals.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé