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From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Igor Mammedov <imammedo@redhat.com>, Tao Su <tao1.su@linux.intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, lei4.wang@intel.com,
	qian.wen@intel.com
Subject: Re: [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids
Date: Tue, 27 Jun 2023 13:54:23 +0800	[thread overview]
Message-ID: <c18ebbaf-0ea8-3cd5-9fb8-6e63add59fba@intel.com> (raw)
In-Reply-To: <20230626145610.64405831@imammedo.users.ipa.redhat.com>

On 6/26/2023 8:56 PM, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:10 +0800
> Tao Su<tao1.su@linux.intel.com>  wrote:
> 
>> From: Qian Wen<qian.wen@intel.com>
>>
>> Emerald Rapids (EMR) is the next generation of Xeon server processor
>> after Sapphire Rapids (SPR).
>>
>> Currently, regarding the feature set that can be exposed to guest, there
>> isn't any one new comparing with SPR cpu model, except that EMR has a
>> different model number.
>>
>> Though it's practicable to define EMR as an alias of a new version of
>> SPR by only updating the model number and model name, it loses the
>> flexibility when new version of EMR cpu model are needed for adding new
>> features (that hasn't virtalized/supported by KVM yet).
> Which begs a question, why do we need EMR model (or alias) at all
> if it's the same as SPR at the moment.
> 
> Make new features supported 1st and only then introduce a new CPU model.
> 

Even if no new feature (that can be virtualized and exposed to guest) in 
EMR compared to SPR in the end, I think it still makes sense to provide 
a dedicated EMR CPU model in QEMU. Because
1) User will know EMR, Intel's next generation of Xeon after SRP, is 
supported by QEMU, via -cpu ?/ -cpu help;
2) It's convenient for user to create an EMR VM. People may not care 
that much what the difference between "-cpu SapphireRapids" with "-cpu 
EmeraldRapids", while they do want to create an VM which shows the CPU 
is EmeraldRapids.



  reply	other threads:[~2023-06-27  5:55 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-16  3:23 [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Tao Su
2023-06-16  3:23 ` [PATCH 1/7] target/i386: Add FEAT_7_1_EDX to adjust feature level Tao Su
2023-06-26 12:39   ` Igor Mammedov
2023-06-27  4:27     ` Tao Su
2023-06-27  8:28       ` Igor Mammedov
2023-06-16  3:23 ` [PATCH 2/7] target/i386: Add support for MCDT_NO in CPUID enumeration Tao Su
2023-06-16  3:23 ` [PATCH 3/7] target/i386: Allow MCDT_NO if host supports Tao Su
2023-06-26 13:03   ` Igor Mammedov
2023-06-27  4:31     ` Tao Su
2023-06-16  3:23 ` [PATCH 4/7] target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES Tao Su
2023-06-26 13:12   ` Igor Mammedov
2023-06-16  3:23 ` [PATCH 5/7] target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model Tao Su
2023-06-26 13:15   ` Igor Mammedov
2023-06-27  6:10     ` Xiaoyao Li
2023-06-27  8:29       ` Igor Mammedov
2023-06-16  3:23 ` [PATCH 6/7] target/i386: Add new CPU model EmeraldRapids Tao Su
2023-06-26 12:56   ` Igor Mammedov
2023-06-27  5:54     ` Xiaoyao Li [this message]
2023-06-27  8:49       ` Igor Mammedov
2023-06-27 11:25         ` Xiaoyao Li
2023-06-27 11:34           ` Daniel P. Berrangé
2023-06-16  3:23 ` [PATCH 7/7] target/i386: Add new CPU model GraniteRapids Tao Su
2023-06-27 11:55   ` Igor Mammedov
2023-06-28  6:11     ` Tao Su
2023-06-16  4:01 ` [PATCH 0/7] Add new CPU model EmeraldRapids and GraniteRapids Wang, Lei
2023-06-16  4:22   ` Tao Su

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