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([2804:431:c7c6:daa8:ba9e:6f18:bac1:8a96]) by smtp.gmail.com with ESMTPSA id q9-20020a4ae649000000b00320d35fc91dsm1252239oot.24.2022.03.24.06.10.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Mar 2022 06:10:22 -0700 (PDT) Message-ID: Date: Thu, 24 Mar 2022 10:10:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 2/2] ppc/pnv: Remove LSI on the PCIE host bridge Content-Language: en-US To: Frederic Barrat , clg@kaod.org, mst@redhat.com, marcel.apfelbaum@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20220321153357.165775-1-fbarrat@linux.ibm.com> <20220321153357.165775-3-fbarrat@linux.ibm.com> From: Daniel Henrique Barboza In-Reply-To: <20220321153357.165775-3-fbarrat@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22d (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/21/22 12:33, Frederic Barrat wrote: > The phb3/phb4/phb5 root ports inherit from the default PCIE root port > implementation, which requests a LSI interrupt (#INTA). On real > hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch > corrects it so that it matches the hardware. > > As a consequence, the device tree previously generated was bogus, as > the root bridge LSI was not properly mapped. On some > implementation (powernv9), it was leading to inconsistent interrupt > controller (xive) data. With this patch, it is now clean. > > Signed-off-by: Frederic Barrat > --- Reviewed-by: Daniel Henrique Barboza > hw/pci-host/pnv_phb3.c | 1 + > hw/pci-host/pnv_phb4.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c > index ac801ac835..0d18c96117 100644 > --- a/hw/pci-host/pnv_phb3.c > +++ b/hw/pci-host/pnv_phb3.c > @@ -1162,6 +1162,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) > error_propagate(errp, local_err); > return; > } > + pci_config_set_interrupt_pin(pci->config, 0); > } > > static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index b301762093..b66b75d4d7 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -1772,6 +1772,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev) > pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); > pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ > pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); > + pci_config_set_interrupt_pin(conf, 0); > } > > static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)