From: Richard Henderson <richard.henderson@linaro.org>
To: Taylor Simpson <tsimpson@quicinc.com>, qemu-devel@nongnu.org
Cc: philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com,
quic_mathbern@quicinc.com
Subject: Re: [PATCH 04/21] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe
Date: Wed, 26 Apr 2023 18:39:56 +0100 [thread overview]
Message-ID: <c2569a8f-c8f2-f645-339a-8efa4db74b76@linaro.org> (raw)
In-Reply-To: <20230426004130.1318973-1-tsimpson@quicinc.com>
On 4/26/23 01:41, Taylor Simpson wrote:
> +#ifndef CONFIG_HEXAGON_IDEF_PARSER
> +/* frame = ((LR << 32) | FP) ^ (FRAMEKEY << 32)) */
> +static void gen_frame_scramble(TCGv_i64 result)
> +{
> + TCGv_i64 framekey = tcg_temp_new_i64();
> + tcg_gen_extu_i32_i64(framekey, hex_gpr[HEX_REG_FRAMEKEY]);
> + tcg_gen_shli_i64(framekey, framekey, 32);
> + tcg_gen_concat_i32_i64(result, hex_gpr[HEX_REG_FP], hex_gpr[HEX_REG_LR]);
> + tcg_gen_xor_i64(result, result, framekey);
> +}
> +#endif
Better as
tmp = tcg_temp_new_i32();
tcg_gen_xor_i32(tmp, hex_gpr[HEX_REG_LR], hex_gpr[HEX_REG_FRAMEKEY]);
tcg_gen_concat_i32_i64(result, hex_gpr[HEX_REG_FRAMEKEY], tmp);
> +#ifndef CONFIG_HEXAGON_IDEF_PARSER
> +/* Stack overflow check */
> +static void gen_framecheck(TCGv EA, int framesize)
> +{
> + /* Not modelled in linux-user mode */
> + /* Placeholder for system mode */
> +}
g_assert_not_reached();
> + TCGv_i64 frame = tcg_temp_new_i64();
> + tcg_gen_addi_tl(r30, r29, -8);
> + gen_frame_scramble(frame);
Perhaps better as
TCGv_i64 frame = gen_frame_scramble();
with the allocation inside the subroutine.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2023-04-26 17:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 0:41 [PATCH 04/21] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe Taylor Simpson
2023-04-26 17:39 ` Richard Henderson [this message]
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