From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>, Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt()
Date: Thu, 13 Aug 2020 08:52:43 -0700 [thread overview]
Message-ID: <c2624d4f-41f9-8a84-9694-7897cd80c2d0@linaro.org> (raw)
In-Reply-To: <CAKmqyKMCYutR5TNvbJ3nA0rAu4W0xFVsZRm66W7Fi_Nw3joiBw@mail.gmail.com>
On 8/12/20 4:16 PM, Alistair Francis wrote:
> I don't like that we have to manually decode the instructions. As it's
> only a handful it's not the end of the world, but it seems like
> duplication that could grow. Could we not use decode_insn16() instead?
> That way we can share the well tested TCG decoder.
Certainly. Compare how the decoder can be re-purposed for disassembly -- e.g.
target/openrisc/disas.c.
Perhaps something like
typedef uint32_t DisasContext;
#include "decode_insn16.inc.c"
/*
* This function is supposed to be called for an instruction
* that has already executed, and thus is known to be valid.
* That said, return 0 for an invalid instruction.
*/
uint32_t riscv_expand_rvc_to_rvi(uint16_t insn16)
{
uint32_t insn32 = 0; /* illegal instruction */
decode_insn16(&insn32, insn16);
return insn32;
}
static bool expand_i(DisasContext *ctx, arg_immi *a,
uint32_t insn32)
{
insn32 = SET_RD(insn32, a->rd);
insn32 = SET_RS1(insn32, a->rs1);
insn32 = SET_I_IMM(insn32, a->imm);
*ctx = insn32;
return true;
}
static bool trans_addi(DisasContext *ctx, arg_immi *a)
{
return expand_i(ctx, a, OPC_RISC_ADDI);
}
etc. All placed in a new file, so that the myriad symbols don't conflict with
anything else.
r~
prev parent reply other threads:[~2020-08-13 15:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel
2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel
2020-08-12 22:37 ` Alistair Francis
2020-07-29 11:28 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Anup Patel
2020-08-10 22:37 ` Alistair Francis
2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel
2020-08-12 23:16 ` Alistair Francis
2020-08-13 15:52 ` Richard Henderson [this message]
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