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Tue, 02 Dec 2025 06:29:10 -0800 (PST) Received: from [192.168.0.102] ([177.139.2.175]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-55cf4e1d580sm6506596e0c.1.2025.12.02.06.29.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Dec 2025 06:29:10 -0800 (PST) Message-ID: Date: Tue, 2 Dec 2025 11:29:08 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2 To: Jim MacArthur , qemu-devel@nongnu.org, Richard Henderson References: <20251202120250.763150-1-jim.macarthur@linaro.org> <20251202120250.763150-3-jim.macarthur@linaro.org> Content-Language: en-US From: Gustavo Romero In-Reply-To: <20251202120250.763150-3-jim.macarthur@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::a36; envelope-from=gustavo.romero@linaro.org; helo=mail-vk1-xa36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jim, On 12/2/25 09:00, Jim MacArthur wrote: > This just allows read/write of three feature bits. ASID is still > ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing > the ASID, will still cause a complete flush of the TLB. > > Signed-off-by: Jim MacArthur > --- > target/arm/cpu-features.h | 7 +++++++ > target/arm/helper.c | 6 ++++++ > 2 files changed, 13 insertions(+) > > diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h > index 579fa8f8f4..d56bda9ce0 100644 > --- a/target/arm/cpu-features.h > +++ b/target/arm/cpu-features.h > @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) > FIELD(ID_AA64MMFR3, ADERR, 56, 4) > FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) > > +FIELD(ID_AA64MMFR4, ASID2, 8, 4) > + > FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) > FIELD(ID_AA64DFR0, TRACEVER, 4, 4) > FIELD(ID_AA64DFR0, PMUVER, 8, 4) > @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMISARegisters *id) > return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0; > } > > +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) > +{ > + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) != 0; > +} > + > static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) > { > return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index c20334fa65..7812a82bab 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, > if (cpu_isar_feature(aa64_aie, cpu)) { > valid_mask |= TCR2_AIE; > } > + if (cpu_isar_feature(aa64_asid2, cpu)) { > + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; > + } > value &= valid_mask; > raw_write(env, ri, value); > } > @@ -6121,6 +6124,9 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, > if (cpu_isar_feature(aa64_mec, cpu)) { > valid_mask |= TCR2_AMEC0 | TCR2_AMEC1; > } > + if (cpu_isar_feature(aa64_asid2, cpu)) { > + valid_mask |= TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; > + } > value &= valid_mask; > raw_write(env, ri, value); > } Afaics, we are not flushing the TLB here like we do for TCR_ELx (in vmsa_tcr_el12_write) before we call raw_write(). Since here we could be changing the A2 & friends bits, which can change the value of the ASID being using (like the TCR_ELx.A1 bit), I believe we should flush the TLB explicitly here like we do in vmsa_tcr_el12_write(). @rth wdyt? Cheers, Gustavo