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Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Xiaoyao Li Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhenyu Wang , Zhuocheng Ding , Yongwei Ma , Zhao Liu References: <20240227103231.1556302-1-zhao1.liu@linux.intel.com> <20240227103231.1556302-8-zhao1.liu@linux.intel.com> From: "Moger, Babu" In-Reply-To: <20240227103231.1556302-8-zhao1.liu@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DS7PR03CA0077.namprd03.prod.outlook.com (2603:10b6:5:3bb::22) To MW3PR12MB4553.namprd12.prod.outlook.com (2603:10b6:303:2c::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW3PR12MB4553:EE_|DM4PR12MB8500:EE_ X-MS-Office365-Filtering-Correlation-Id: 07a54063-9dd8-4996-a6d7-08dc393908bd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nMPfkYYjTG033Uf2yRiJuf5ZdpEKNWxyjUNcRTAiNFFSFct/f36yp/QcYAxOK35utAnYtinrs0BupxTA7meWrz4JAuX7im5L/VPsvGXfaEK5fKT8ObCJrJkDomaaJPnXh36d0thsmDNhO9FQI4sQ0D83zyBaWbgAbojK1QS0vRJz4ft3CYzRssrk7TtfVb2t43wBQJfEcH249zCwM8Aiq3YjIF+gBFoBRL1nml6T72V00W1P1fhAruXQHsBPIu/vdJobhSh2fNT2cXocalfIA4fNLH0IeSGdZTQRb98NyvifwymB0WyluJOC49lfkluC2ot3wvjHQ012KYoqQ//mzk2n7CAoDPXlTIXH0iZaddn74RCK41E6LO389HgXxXjHxVMSXdbleT9/WRpYzTlJQkG0thNOyz8QoRJ6uW30xfJPvqNw+3qLmzoxKYmihzcQ4ye/2Rw8s9oAxkmCil4Y/dj0kPOYyAWaLBN48+6YLPSUrM0j9GyNczNkimV68cGD3ovDJ3xSE/yv7RGRnL2lfOO9ZMoYhYViWYZ4Ty+Ju+ajkX5MuF39Lj0TRm8HSKiy/n+wgQIc1Ozah3UxAgz+mjKkOB8mynliH5sX4zxojDRaLOe57ejdC+YwoOsrSCjvWSHdD1WlFeEyZDhwQy3G11Q85EZ4G97y0+80eoKt9GLkFpoqUxLE2I+J89660OQPtQ2qBWYAOrZuQ4j4fHe2wg== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=Babu.Moger@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.096, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: babu.moger@amd.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/27/24 04:32, Zhao Liu wrote: > From: Zhao Liu > > The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information > for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding > the number of sharing threads directly. > > From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) > means [1]: > > The number of logical processors sharing this cache is the value of > this field incremented by 1. To determine which logical processors are > sharing a cache, determine a Share Id for each processor as follows: > > ShareId = LocalApicId >> log2(NumSharingCache+1) > > Logical processors with the same ShareId then share a cache. If > NumSharingCache+1 is not a power of two, round it up to the next power > of two. > > From the description above, the calculation of this field should be same > as CPUID[4].EAX[bits 25:14] for Intel CPUs. So also use the offsets of > APIC ID to calculate this field. > > [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology > Information > > Cc: Babu Moger > Tested-by: Yongwei Ma > Signed-off-by: Zhao Liu Reviewed-by: Babu Moger > --- > Changes since v7: > * Moved this patch after CPUID[4]'s similar change ("i386/cpu: Use APIC > ID offset to encode cache topo in CPUID[4]"). (Xiaoyao) > * Dropped Michael/Babu's Acked/Reviewed/Tested tags since the code > change due to the rebase. > * Re-added Yongwei's Tested tag For his re-testing (compilation on > Intel platforms). > > Changes since v3: > * Rewrote the subject. (Babu) > * Deleted the original "comment/help" expression, as this behavior is > confirmed for AMD CPUs. (Babu) > * Renamed "num_apic_ids" (v3) to "num_sharing_cache" to match spec > definition. (Babu) > > Changes since v1: > * Renamed "l3_threads" to "num_apic_ids" in > encode_cache_cpuid8000001d(). (Yanan) > * Added the description of the original commit and add Cc. > --- > target/i386/cpu.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index c77bcbc44d59..df56c7a449c8 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -331,7 +331,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > uint32_t *eax, uint32_t *ebx, > uint32_t *ecx, uint32_t *edx) > { > - uint32_t l3_threads; > + uint32_t num_sharing_cache; > assert(cache->size == cache->line_size * cache->associativity * > cache->partitions * cache->sets); > > @@ -340,11 +340,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, > > /* L3 is shared among multiple cores */ > if (cache->level == 3) { > - l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; > - *eax |= (l3_threads - 1) << 14; > + num_sharing_cache = 1 << apicid_die_offset(topo_info); > } else { > - *eax |= ((topo_info->threads_per_core - 1) << 14); > + num_sharing_cache = 1 << apicid_core_offset(topo_info); > } > + *eax |= (num_sharing_cache - 1) << 14; > > assert(cache->line_size > 0); > assert(cache->partitions > 0); -- Thanks Babu Moger