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([2602:ae:1543:f001:b25a:9949:8352:ec5d]) by smtp.gmail.com with ESMTPSA id rm10-20020a17090b3eca00b001df264610c4sm11513383pjb.0.2022.06.24.07.16.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jun 2022 07:17:00 -0700 (PDT) Message-ID: Date: Fri, 24 Jun 2022 07:16:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v3 30/51] target/arm: Implement FMOPA, FMOPS (non-widening) Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220620175235.60881-1-richard.henderson@linaro.org> <20220620175235.60881-31-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/24/22 05:31, Peter Maydell wrote: > On Mon, 20 Jun 2022 at 19:07, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson > >> +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, >> + void *vpm, void *vst, uint32_t desc) >> +{ >> + intptr_t row, col, oprsz = simd_maxsz(desc); >> + uint32_t neg = simd_data(desc) << 31; >> + uint16_t *pn = vpn, *pm = vpm; >> + >> + bool save_dn = get_default_nan_mode(vst); >> + set_default_nan_mode(true, vst); >> + >> + for (row = 0; row < oprsz; ) { >> + uint16_t pa = pn[H2(row >> 4)]; >> + do { >> + if (pa & 1) { >> + void *vza_row = vza + row * sizeof(ARMVectorReg); >> + uint32_t n = *(uint32_t *)(vzn + row) ^ neg; >> + >> + for (col = 0; col < oprsz; ) { >> + uint16_t pb = pm[H2(col >> 4)]; >> + do { >> + if (pb & 1) { >> + uint32_t *a = vza_row + col; >> + uint32_t *m = vzm + col; >> + *a = float32_muladd(n, *m, *a, 0, vst); >> + } >> + col += 4; >> + pb >>= 4; >> + } while (col & 15); >> + } >> + } >> + row += 4; >> + pa >>= 4; >> + } while (row & 15); >> + } > > The code for the double version seems straightforward: > row counts from 0 up to the number of rows, and we > do something per row. Why is the single precision version > doing something with an unrolled loop here? It's confusing > that 'oprsz' in the two functions isn't the same thing -- > in the double version we divide by the element size, but > here we don't. It's all about the predicate addressing. For doubles, the bits are spaced 8 bits apart, which makes it easy as you see. For singles, the bits are spaced 4 bits apart, which is inconvenient. Anyway, just as over in sve_helper.c, I load uint16_t at a time and shift to find each predicate bit. So it's not unrolled, exactly. There's second loop over predicates. And since this is a matrix op, we get loops nested 4 deep. > The pseudocode says that we ignore floating point exceptions > (ie do not accumulate them in the FPSR) -- it passes fpexc == false > to FPMulAdd(). Don't we need to do something special to arrange > for that ? Oops, somewhere I read that as "do not trap" not "do not accumulate". But R_TGSKG is very clear on this as accumulate. r~