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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db10b2fsm62443835e9.33.2025.02.06.10.37.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 10:37:09 -0800 (PST) Message-ID: Date: Thu, 6 Feb 2025 19:37:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Michal Simek Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Anton Johansson , Jason Wang , Paolo Bonzini , Alistair Francis , Thomas Huth , Richard Henderson , Peter Maydell , Markus Armbruster , =?UTF-8?Q?Alex_Benn=C3=A9e?= , "Edgar E. Iglesias" References: <20250206131052.30207-1-philmd@linaro.org> <20250206131052.30207-12-philmd@linaro.org> <4624f149-76d0-4da5-8f13-8c015043c335@linaro.org> <3156dc3b-9553-4b5f-a934-f29ee0601887@linaro.org> <63f1130e-a30d-4416-ae74-374f1fd94dbe@linaro.org> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org (sorry, posted too quick) On 6/2/25 19:24, Philippe Mathieu-Daudé wrote: > +Michal > > On 6/2/25 19:06, Daniel P. Berrangé wrote: >> On Thu, Feb 06, 2025 at 06:49:38PM +0100, Philippe Mathieu-Daudé wrote: >>> On 6/2/25 18:12, Daniel P. Berrangé wrote: >>>> On Thu, Feb 06, 2025 at 04:04:20PM +0100, Philippe Mathieu-Daudé wrote: >>>>> On 6/2/25 15:31, Daniel P. Berrangé wrote: >>>>>> On Thu, Feb 06, 2025 at 02:53:58PM +0100, Philippe Mathieu-Daudé >>>>>> wrote: >>>>>>> Hi Daniel, >>>>>>> >>>>>>> On 6/2/25 14:20, Daniel P. Berrangé wrote: >>>>>>>> On Thu, Feb 06, 2025 at 02:10:47PM +0100, Philippe Mathieu-Daudé >>>>>>>> wrote: >>>>>>>>> Introduce an abstract machine parent class which defines >>>>>>>>> the 'little_endian' property. Duplicate the current machine, >>>>>>>>> which endian is tied to the binary endianness, to one big >>>>>>>>> endian and a little endian machine; updating the machine >>>>>>>>> description. Keep the current default machine for each binary. >>>>>>>>> >>>>>>>>> 'petalogix-s3adsp1800' machine is aliased as: >>>>>>>>> - 'petalogix-s3adsp1800-be' on big-endian binary, >>>>>>>>> - 'petalogix-s3adsp1800-le' on little-endian one. >>>>>>>> >>>>>>>> Does it makes sense to expose these as different machine types ? >>>>>>>> >>>>>>>> If all the HW is identical in both cases, it feels like the >>>>>>>> endianness could just be a bool property of the machine type, >>>>>>>> rather than a new machine type. >>>>>>> >>>>>>> Our test suites expect "qemu-system-foo -M bar" to work out of >>>>>>> the box, we can not have non-default properties. >>>>>>> >>>>>>> (This is related to the raspberry pi discussion in >>>>>>> https://lore.kernel.org/qemu-devel/20250204002240.97830-1- >>>>>>> philmd@linaro.org/). >>>>>>> >>>>>>> My plan is to deprecate 'petalogix-s3adsp1800', so once we >>>>>>> remove it we can merge both qemu-system-microblaze and >>>>>>> qemu-system-microblazeel into a single binary. >>>>>>> >>>>>>> If you don't want to add more machines, what should be the >>>>>>> endianness of the 'petalogix-s3adsp1800' machine in a binary >>>>>>> with no particular endianness? Either we add for explicit >>>>>>> endianness (fixing test suites) or we add one machine for >>>>>>> each endianness; I fail to see other options not too >>>>>>> confusing for our users. >>>>>> >>>>>> We would pick an arbitrary endianness of our choosing >>>>>> I guess. How does this work in physical machines ? Is >>>>>> the choice of endianess a firmware setting, or a choice >>>>>> by the vendor when manufacturing in some way ? >>>>> >>>>> Like MIPS*, SH4* and Xtensa*, it is a jumper on the board >>>>> (wired to a CPU pin which is sampled once at cold reset). >>>> >>>> That makes me thing even more it is just a machine type property. >>> >>> I'm happy with a machine property, this was even my first approach >>> using OnOffAuto until I ran the test-suite and have qom-introspection >>> failing. >>> >>> What should be the default? >>> >>> Per the SH4 datasheet: >>> >>>    Bit 31—Endian Flag (ENDIAN): Samples the value of the endian >>>    specification external pin (MD5) in a power-on reset by the >>>    RESET pin. The endian mode of all spaces is determined by this >>>    bit. ENDIAN is a read-only bit. >>> >>> There is no default per the spec, and I believe using one is >>> a mistake. >> >> If it is left as an unspecified choice in the spec, then I would >> presume HW vendors are picking an option based on what they >> expect "most" common usage to be amongst their customers. IOW, >> if we know of typically used guest OS prefer big or little, that >> could influence our choice. > > Please have a look at this thread: > https://lore.kernel.org/qemu-devel/ > d3346a55-584b-427b-8c87-32f7411a9290@amd.com/ Per Michal: Truth is that I am not aware about anybody configuring MB to big endian and we are on AXI for quite a long time. There is still code in Linux kernel for it but I can't see any reason to keep it around. I don't think that make sense to keep big endian configurations alive at all. So with that in mind, using a default of little-endian=true for MicroBlaze seems safe as of 2025. For MIPS, big-endian was the default but as the industry shifted, it stayed big-endian on low-end 32-bit cores but mostly became little-endian on high-end 64-bit cores. For Renesas RX, the "Endian" section in the "CPU" chapter of the hardware manual mentions: Both big and little endian are supported for the treatment of data, and the endian is switched by changing the setting on a mode pin (MDE) at the time of a power-on reset. SH-4 "is bi-endian, running in either big-endian or little-endian byte ordering."