* [Qemu-devel] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev @ 2019-07-18 12:44 Ivan Warren via Qemu-devel 2019-07-18 17:19 ` Greg Kurz 0 siblings, 1 reply; 5+ messages in thread From: Ivan Warren via Qemu-devel @ 2019-07-18 12:44 UTC (permalink / raw) Cc: Greg Kurz, qemu-ppc, qemu-devel, david [-- Attachment #1: Type: text/plain, Size: 1730 bytes --] Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030. Per this specification, bit 15 is implementation specific so it may be 1, but can probably ne safely ignored. Power ISA 2.07B (Power 7/Power 8) indicates the bit is reserved but some none Linux operating systems do set this bit to 1 when entering the debugger. So it is likely it is implemented on those systems but wasn't yet documented. Signed-off-by: Ivan Warren <ivan@vmfacility.fr> --- The original creator of the patch is "Zhuowei Zhang" (https://twitter.com/zhuowei) but I couldn't find any e-mail address. target/ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4a5de28036..85f8b147ba 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, PPC_SEGMENT_64B), +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), #endif GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), -- 2.20.1 [-- Attachment #2: Signature cryptographique S/MIME --] [-- Type: application/pkcs7-signature, Size: 3997 bytes --] ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev 2019-07-18 12:44 [Qemu-devel] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev Ivan Warren via Qemu-devel @ 2019-07-18 17:19 ` Greg Kurz 2019-07-18 20:15 ` [Qemu-devel] [Qemu-ppc] " Ivan Warren via Qemu-devel 0 siblings, 1 reply; 5+ messages in thread From: Greg Kurz @ 2019-07-18 17:19 UTC (permalink / raw) To: Ivan Warren; +Cc: qemu-ppc, qemu-devel, david We usually mention the subsystem name in the subject, ie. target/ppc: Allow bit 15 to be set to 1 on slbmfee and slbmfev On Thu, 18 Jul 2019 14:44:49 +0200 Ivan Warren <ivan@vmfacility.fr> wrote: > Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG > as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030. > Per this specification, bit 15 is implementation specific > so it may be 1, but can probably ne safely ignored. > > Power ISA 2.07B (Power 7/Power 8) indicates the bit is > reserved but some none Linux operating systems do set s/none Linux/non-Linux > this bit to 1 when entering the debugger. > So it is likely it is implemented on those systems > but wasn't yet documented. > ISA describes things that are common to several processor types, but each implementation may do some extra stuff... like giving a special meaning to an invalid instruction form for example (see commit fa200c95f7f99ce14b8af25ea0be478c722d3cec). This is supposed to be documented in the user manual. Maybe something similar was done with the reserved bit 15, even if I could fine no trace of that in the Power8 UM... of course. I'll try to find clues within IBM. https://openpowerfoundation.org/?resource_lib=power8-processor-users-manual but it is indeed mentioned in the Power9 UM: https://openpowerfoundation.org/?resource_lib=power-processor-users-manual 4.10.7.2 SLB Management Instructions The POWER9 core implements the SLB management instructions as defined in the Power ISA (Version 3.0B). Specifically, the following instruction details are noteworthy: • The slbmfee and slbmfev instructions can read any SLB entry when UPRT = ‘1’, if the L-bit in the instruction image is set to a ‘1’. This is an implementation-specific feature that will only be used in the future if and when the POWER9 processor core supports UPRT = ‘1’ for HPT translation. Not sure if we support that in TCG, but it doesn't hurt to relax the check if that's enough to make AIX's debugger happy. Reviewed-by: Greg Kurz <groug@kaod.org> > Signed-off-by: Ivan Warren <ivan@vmfacility.fr> > --- > > The original creator of the patch is "Zhuowei Zhang" > (https://twitter.com/zhuowei) but I couldn't find any e-mail address. > This is the original patch, correct ? https://github.com/zhuowei/qemu/commit/c5f305c5d0cd336b2bb31cab8a70f90b72905a1e After speaking with some QEMU folks on irc, it is okay to ignore the lack of S-o-b because the patch is trivial. But the general rule is to always require an S-o-b when posting someone else's patch. > target/ppc/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 4a5de28036..85f8b147ba 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, > 0x0010F801, PPC_SEGMENT_64B), > GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, > PPC_SEGMENT_64B), > GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, > PPC_SEGMENT_64B), > -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, > PPC_SEGMENT_64B), > -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, > PPC_SEGMENT_64B), > +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, > PPC_SEGMENT_64B), > +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, > PPC_SEGMENT_64B), > GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, > PPC_SEGMENT_64B), > #endif > GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), > -- > 2.20.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev 2019-07-18 17:19 ` Greg Kurz @ 2019-07-18 20:15 ` Ivan Warren via Qemu-devel 2019-07-19 1:34 ` David Gibson 0 siblings, 1 reply; 5+ messages in thread From: Ivan Warren via Qemu-devel @ 2019-07-18 20:15 UTC (permalink / raw) To: Greg Kurz; +Cc: qemu-ppc, qemu-devel, david [-- Attachment #1: Type: text/plain, Size: 4416 bytes --] Le 7/18/2019 à 7:19 PM, Greg Kurz a écrit : > We usually mention the subsystem name in the subject, ie. > > target/ppc: Allow bit 15 to be set to 1 on slbmfee and slbmfev Gotcha ! Still learning the process as I go. Next time I submit something, I'll follow the guidelines more accurately. > > On Thu, 18 Jul 2019 14:44:49 +0200 > Ivan Warren <ivan@vmfacility.fr> wrote: > >> Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG >> as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030. >> Per this specification, bit 15 is implementation specific >> so it may be 1, but can probably ne safely ignored. Another typo from me ! s/ne safely/be safely/ >> >> Power ISA 2.07B (Power 7/Power 8) indicates the bit is >> reserved but some none Linux operating systems do set > s/none Linux/non-Linux Thanks ! Sorry for the typo ! > >> this bit to 1 when entering the debugger. >> So it is likely it is implemented on those systems >> but wasn't yet documented. >> > ISA describes things that are common to several processor types, > but each implementation may do some extra stuff... like giving > a special meaning to an invalid instruction form for example (see > commit fa200c95f7f99ce14b8af25ea0be478c722d3cec). This is supposed > to be documented in the user manual. > > Maybe something similar was done with the reserved bit 15, even if I > could fine no trace of that in the Power8 UM... of course. I'll try > to find clues within IBM. > > https://openpowerfoundation.org/?resource_lib=power8-processor-users-manual > > but it is indeed mentioned in the Power9 UM: > > https://openpowerfoundation.org/?resource_lib=power-processor-users-manual > > 4.10.7.2 SLB Management Instructions > > The POWER9 core implements the SLB management instructions as defined in the > Power ISA (Version 3.0B). Specifically, the following instruction details are > noteworthy: > • The slbmfee and slbmfev instructions can read any SLB entry when UPRT = ‘1’, > if the L-bit in the instruction image is set to a ‘1’. This is an > implementation-specific feature that will only be used in the future if and > when the POWER9 processor core supports UPRT = ‘1’ for HPT translation. > > Not sure if we support that in TCG, but it doesn't hurt to relax the check > if that's enough to make AIX's debugger happy. Yep ! > > Reviewed-by: Greg Kurz <groug@kaod.org> > >> Signed-off-by: Ivan Warren <ivan@vmfacility.fr> >> --- >> >> The original creator of the patch is "Zhuowei Zhang" >> (https://twitter.com/zhuowei) but I couldn't find any e-mail address. >> > This is the original patch, correct ? > > https://github.com/zhuowei/qemu/commit/c5f305c5d0cd336b2bb31cab8a70f90b72905a1e Indeed ! > > After speaking with some QEMU folks on irc, it is okay to ignore the lack > of S-o-b because the patch is trivial. But the general rule is to always > require an S-o-b when posting someone else's patch. Is it good practice to add a S-o-b without the original author's consent and/or without an e-mail address ? Although I would very much doubt he would have complained. Anyway, thanks for reviewing and for the tips ! (and sorry for all the noise). > >> target/ppc/translate.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >> index 4a5de28036..85f8b147ba 100644 >> --- a/target/ppc/translate.c >> +++ b/target/ppc/translate.c >> @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, >> 0x0010F801, PPC_SEGMENT_64B), >> GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, >> PPC_SEGMENT_64B), >> GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, >> PPC_SEGMENT_64B), >> -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, >> PPC_SEGMENT_64B), >> -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, >> PPC_SEGMENT_64B), >> +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, >> PPC_SEGMENT_64B), >> +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, >> PPC_SEGMENT_64B), >> GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, >> PPC_SEGMENT_64B), >> #endif >> GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), >> -- >> 2.20.1 >> >> [-- Attachment #2: Signature cryptographique S/MIME --] [-- Type: application/pkcs7-signature, Size: 3997 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev 2019-07-18 20:15 ` [Qemu-devel] [Qemu-ppc] " Ivan Warren via Qemu-devel @ 2019-07-19 1:34 ` David Gibson 2019-07-19 8:10 ` Ivan Warren via Qemu-devel 0 siblings, 1 reply; 5+ messages in thread From: David Gibson @ 2019-07-19 1:34 UTC (permalink / raw) To: Ivan Warren; +Cc: qemu-ppc, Greg Kurz, qemu-devel [-- Attachment #1: Type: text/plain, Size: 4957 bytes --] On Thu, Jul 18, 2019 at 10:15:52PM +0200, Ivan Warren wrote: > > Le 7/18/2019 à 7:19 PM, Greg Kurz a écrit : > > We usually mention the subsystem name in the subject, ie. > > > > target/ppc: Allow bit 15 to be set to 1 on slbmfee and slbmfev > Gotcha ! Still learning the process as I go. Next time I submit something, > I'll follow the guidelines more accurately. > > > > On Thu, 18 Jul 2019 14:44:49 +0200 > > Ivan Warren <ivan@vmfacility.fr> wrote: > > > > > Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG > > > as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030. > > > Per this specification, bit 15 is implementation specific > > > so it may be 1, but can probably ne safely ignored. > > Another typo from me ! > > s/ne safely/be safely/ > > > > > > > Power ISA 2.07B (Power 7/Power 8) indicates the bit is > > > reserved but some none Linux operating systems do set > > s/none Linux/non-Linux > Thanks ! Sorry for the typo ! > > > > > this bit to 1 when entering the debugger. > > > So it is likely it is implemented on those systems > > > but wasn't yet documented. > > > > > ISA describes things that are common to several processor types, > > but each implementation may do some extra stuff... like giving > > a special meaning to an invalid instruction form for example (see > > commit fa200c95f7f99ce14b8af25ea0be478c722d3cec). This is supposed > > to be documented in the user manual. > > > > Maybe something similar was done with the reserved bit 15, even if I > > could fine no trace of that in the Power8 UM... of course. I'll try > > to find clues within IBM. > > > > https://openpowerfoundation.org/?resource_lib=power8-processor-users-manual > > > > but it is indeed mentioned in the Power9 UM: > > > > https://openpowerfoundation.org/?resource_lib=power-processor-users-manual > > > > 4.10.7.2 SLB Management Instructions > > > > The POWER9 core implements the SLB management instructions as defined in the > > Power ISA (Version 3.0B). Specifically, the following instruction details are > > noteworthy: > > • The slbmfee and slbmfev instructions can read any SLB entry when UPRT = ‘1’, > > if the L-bit in the instruction image is set to a ‘1’. This is an > > implementation-specific feature that will only be used in the future if and > > when the POWER9 processor core supports UPRT = ‘1’ for HPT translation. > > > > Not sure if we support that in TCG, but it doesn't hurt to relax the check > > if that's enough to make AIX's debugger happy. > Yep ! > > > > Reviewed-by: Greg Kurz <groug@kaod.org> > > > > > Signed-off-by: Ivan Warren <ivan@vmfacility.fr> > > > --- > > > > > > The original creator of the patch is "Zhuowei Zhang" > > > (https://twitter.com/zhuowei) but I couldn't find any e-mail address. > > > > > This is the original patch, correct ? > > > > https://github.com/zhuowei/qemu/commit/c5f305c5d0cd336b2bb31cab8a70f90b72905a1e > Indeed ! > > > > After speaking with some QEMU folks on irc, it is okay to ignore the lack > > of S-o-b because the patch is trivial. But the general rule is to always > > require an S-o-b when posting someone else's patch. > > Is it good practice to add a S-o-b without the original author's consent > and/or without an e-mail address ? Absolutely not. > Although I would very much doubt he would > have complained. > > Anyway, thanks for reviewing and for the tips ! (and sorry for all the > noise). > > > > > > target/ppc/translate.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > > > index 4a5de28036..85f8b147ba 100644 > > > --- a/target/ppc/translate.c > > > +++ b/target/ppc/translate.c > > > @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, > > > 0x0010F801, PPC_SEGMENT_64B), > > > GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, > > > PPC_SEGMENT_64B), > > > GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, > > > PPC_SEGMENT_64B), > > > -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, > > > PPC_SEGMENT_64B), > > > -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, > > > PPC_SEGMENT_64B), > > > +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, > > > PPC_SEGMENT_64B), > > > +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, > > > PPC_SEGMENT_64B), > > > GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, > > > PPC_SEGMENT_64B), > > > #endif > > > GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), > -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev 2019-07-19 1:34 ` David Gibson @ 2019-07-19 8:10 ` Ivan Warren via Qemu-devel 0 siblings, 0 replies; 5+ messages in thread From: Ivan Warren via Qemu-devel @ 2019-07-19 8:10 UTC (permalink / raw) To: David Gibson; +Cc: qemu-ppc, Greg Kurz, qemu-devel [-- Attachment #1: Type: text/plain, Size: 5399 bytes --] Le 7/19/2019 à 3:34 AM, David Gibson a écrit : > On Thu, Jul 18, 2019 at 10:15:52PM +0200, Ivan Warren wrote: >> Le 7/18/2019 à 7:19 PM, Greg Kurz a écrit : >>> We usually mention the subsystem name in the subject, ie. >>> >>> target/ppc: Allow bit 15 to be set to 1 on slbmfee and slbmfev >> Gotcha ! Still learning the process as I go. Next time I submit something, >> I'll follow the guidelines more accurately. >>> On Thu, 18 Jul 2019 14:44:49 +0200 >>> Ivan Warren <ivan@vmfacility.fr> wrote: >>> >>>> Allow bit 15 to be 1 in the slbmfee and slbmfev in TCG >>>> as per Power ISA 3.0B (Power 9) Book III pages 1029 and 1030. >>>> Per this specification, bit 15 is implementation specific >>>> so it may be 1, but can probably ne safely ignored. >> Another typo from me ! >> >> s/ne safely/be safely/ >> >>>> Power ISA 2.07B (Power 7/Power 8) indicates the bit is >>>> reserved but some none Linux operating systems do set >>> s/none Linux/non-Linux >> Thanks ! Sorry for the typo ! >>>> this bit to 1 when entering the debugger. >>>> So it is likely it is implemented on those systems >>>> but wasn't yet documented. >>>> >>> ISA describes things that are common to several processor types, >>> but each implementation may do some extra stuff... like giving >>> a special meaning to an invalid instruction form for example (see >>> commit fa200c95f7f99ce14b8af25ea0be478c722d3cec). This is supposed >>> to be documented in the user manual. >>> >>> Maybe something similar was done with the reserved bit 15, even if I >>> could fine no trace of that in the Power8 UM... of course. I'll try >>> to find clues within IBM. >>> >>> https://openpowerfoundation.org/?resource_lib=power8-processor-users-manual >>> >>> but it is indeed mentioned in the Power9 UM: >>> >>> https://openpowerfoundation.org/?resource_lib=power-processor-users-manual >>> >>> 4.10.7.2 SLB Management Instructions >>> >>> The POWER9 core implements the SLB management instructions as defined in the >>> Power ISA (Version 3.0B). Specifically, the following instruction details are >>> noteworthy: >>> • The slbmfee and slbmfev instructions can read any SLB entry when UPRT = ‘1’, >>> if the L-bit in the instruction image is set to a ‘1’. This is an >>> implementation-specific feature that will only be used in the future if and >>> when the POWER9 processor core supports UPRT = ‘1’ for HPT translation. >>> >>> Not sure if we support that in TCG, but it doesn't hurt to relax the check >>> if that's enough to make AIX's debugger happy. >> Yep ! >>> Reviewed-by: Greg Kurz <groug@kaod.org> >>> >>>> Signed-off-by: Ivan Warren <ivan@vmfacility.fr> >>>> --- >>>> >>>> The original creator of the patch is "Zhuowei Zhang" >>>> (https://twitter.com/zhuowei) but I couldn't find any e-mail address. >>>> >>> This is the original patch, correct ? >>> >>> https://github.com/zhuowei/qemu/commit/c5f305c5d0cd336b2bb31cab8a70f90b72905a1e >> Indeed ! >>> After speaking with some QEMU folks on irc, it is okay to ignore the lack >>> of S-o-b because the patch is trivial. But the general rule is to always >>> require an S-o-b when posting someone else's patch. >> Is it good practice to add a S-o-b without the original author's consent >> and/or without an e-mail address ? > Absolutely not. I thought as much (and why I didn't do it). However, I still wanted to give credit (but not a "Signed-off-by:" tag since this didn't actually occur) to the person who originally found the issue (and the fix). I guess it should simply have been included in the commit log as a comment, not as a comment in the patch submission message (between the --- and the actual diff). Anyway, I think the patch is sane and carries no systemic risk (it only affects AIX KBD - and possibly other low level debuggers) - and there are probably no PPC system that actually rely on those instructions throwing an exception if this particular bit is not 0 ! > >> Although I would very much doubt he would >> have complained. >> >> Anyway, thanks for reviewing and for the tips ! (and sorry for all the >> noise). >> >>>> target/ppc/translate.c | 4 ++-- >>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >>>> index 4a5de28036..85f8b147ba 100644 >>>> --- a/target/ppc/translate.c >>>> +++ b/target/ppc/translate.c >>>> @@ -7064,8 +7064,8 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, >>>> 0x0010F801, PPC_SEGMENT_64B), >>>> GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, >>>> PPC_SEGMENT_64B), >>>> GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, >>>> PPC_SEGMENT_64B), >>>> -GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, >>>> PPC_SEGMENT_64B), >>>> -GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, >>>> PPC_SEGMENT_64B), >>>> +GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001E0001, >>>> PPC_SEGMENT_64B), >>>> +GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001E0001, >>>> PPC_SEGMENT_64B), >>>> GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, >>>> PPC_SEGMENT_64B), >>>> #endif >>>> GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), > > [-- Attachment #2: Signature cryptographique S/MIME --] [-- Type: application/pkcs7-signature, Size: 3997 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-07-19 8:10 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-07-18 12:44 [Qemu-devel] [PATCH] Allow bit 15 to be set to 1 on slbmfee and slbmfev Ivan Warren via Qemu-devel 2019-07-18 17:19 ` Greg Kurz 2019-07-18 20:15 ` [Qemu-devel] [Qemu-ppc] " Ivan Warren via Qemu-devel 2019-07-19 1:34 ` David Gibson 2019-07-19 8:10 ` Ivan Warren via Qemu-devel
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