qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Hao Wu <wuhaotsh@google.com>, peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, venture@google.com,
	Avi.Fishman@nuvoton.com, kfting@nuvoton.com,
	hskinnemoen@google.com, titusr@google.com,
	chli30@nuvoton.corp-partner.google.com, pbonzini@redhat.com,
	jasowang@redhat.com, alistair@alistair23.me
Subject: Re: [PATCH v4 13/17] hw/misc: Support NPCM8XX CLK Module Registers
Date: Mon, 10 Feb 2025 15:50:03 +0100	[thread overview]
Message-ID: <c3948f21-bb30-4d43-9b8c-9db1c41f01bd@linaro.org> (raw)
In-Reply-To: <20250206221203.4187217-14-wuhaotsh@google.com>

On 6/2/25 23:11, Hao Wu wrote:
> NPCM8XX adds a few new registers and have a different set of reset
> values to the CLK modules. This patch supports them.
> 
> This patch doesn't support the new clock values generated by these
> registers. Currently no modules use these new clock values so they
> are not necessary at this point.
> Implementation of these clocks might be required when implementing
> these modules.
> 
> Reviewed-by: Titus Rwantare <titusr@google.com>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> ---
>   hw/misc/npcm_clk.c         | 113 +++++++++++++++++++++++++++++++++++--
>   include/hw/misc/npcm_clk.h |  10 +++-
>   2 files changed, 117 insertions(+), 6 deletions(-)


> diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h
> index f47614ac8d..8fa1e14bdd 100644
> --- a/include/hw/misc/npcm_clk.h
> +++ b/include/hw/misc/npcm_clk.h
> @@ -1,5 +1,5 @@
>   /*
> - * Nuvoton NPCM7xx Clock Control Registers.
> + * Nuvoton NPCM7xx/8xx Clock Control Registers.
>    *
>    * Copyright 2020 Google LLC
>    *
> @@ -21,11 +21,12 @@
>   #include "hw/sysbus.h"
>   
>   #define NPCM7XX_CLK_NR_REGS             (0x70 / sizeof(uint32_t))
> +#define NPCM8XX_CLK_NR_REGS             (0xc4 / sizeof(uint32_t))
>   /*
>    * Number of maximum registers in NPCM device state structure. Don't change
>    * this without incrementing the version_id in the vmstate.
>    */
> -#define NPCM_CLK_MAX_NR_REGS            NPCM7XX_CLK_NR_REGS
> +#define NPCM_CLK_MAX_NR_REGS            NPCM8XX_CLK_NR_REGS

This also breaks vmstate_npcm_clk migration.



  reply	other threads:[~2025-02-10 14:50 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 22:11 [PATCH v4 00/17] hw/arm: Add NPCM8XX Support Hao Wu
2025-02-06 22:11 ` [PATCH v4 01/17] roms: Update vbootrom to 1287b6e Hao Wu
2025-02-06 22:11 ` [PATCH v4 02/17] pc-bios: Add NPCM8XX vBootrom Hao Wu
2025-02-06 22:11 ` [PATCH v4 03/17] hw/ssi: Make flash size a property in NPCM7XX FIU Hao Wu
2025-02-10 14:43   ` Philippe Mathieu-Daudé
2025-02-06 22:11 ` [PATCH v4 04/17] hw/misc: Rename npcm7xx_gcr to npcm_gcr Hao Wu
2025-02-06 22:11 ` [PATCH v4 05/17] hw/misc: Move NPCM7XX GCR to NPCM GCR Hao Wu
2025-02-06 22:11 ` [PATCH v4 06/17] hw/misc: Add nr_regs and cold_reset_values " Hao Wu
2025-02-06 22:11 ` [PATCH v4 07/17] hw/misc: Add support for NPCM8XX GCR Hao Wu
2025-02-10 14:47   ` Philippe Mathieu-Daudé
2025-02-06 22:11 ` [PATCH v4 08/17] hw/misc: Store DRAM size in NPCM8XX GCR Module Hao Wu
2025-02-06 22:11 ` [PATCH v4 09/17] hw/misc: Support 8-bytes memop in NPCM GCR module Hao Wu
2025-02-10 14:48   ` Philippe Mathieu-Daudé
2025-02-06 22:11 ` [PATCH v4 10/17] hw/misc: Rename npcm7xx_clk to npcm_clk Hao Wu
2025-02-06 22:11 ` [PATCH v4 11/17] hw/misc: Move NPCM7XX CLK to NPCM CLK Hao Wu
2025-02-06 22:11 ` [PATCH v4 12/17] hw/misc: Add nr_regs and cold_reset_values " Hao Wu
2025-02-06 22:11 ` [PATCH v4 13/17] hw/misc: Support NPCM8XX CLK Module Registers Hao Wu
2025-02-10 14:50   ` Philippe Mathieu-Daudé [this message]
2025-02-06 22:12 ` [PATCH v4 14/17] hw/net: Add NPCM8XX PCS Module Hao Wu
2025-02-06 22:12 ` [PATCH v4 15/17] hw/arm: Add NPCM8XX SoC Hao Wu
2025-02-10 14:52   ` Peter Maydell
2025-02-10 14:53   ` Philippe Mathieu-Daudé
2025-02-06 22:12 ` [PATCH v4 16/17] hw/arm: Add NPCM845 Evaluation board Hao Wu
2025-02-06 22:12 ` [PATCH v4 17/17] docs/system/arm: Add Description for NPCM8XX SoC Hao Wu
2025-02-10 14:30   ` Peter Maydell
2025-02-17 13:44 ` [PATCH v4 00/17] hw/arm: Add NPCM8XX Support Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=c3948f21-bb30-4d43-9b8c-9db1c41f01bd@linaro.org \
    --to=philmd@linaro.org \
    --cc=Avi.Fishman@nuvoton.com \
    --cc=alistair@alistair23.me \
    --cc=chli30@nuvoton.corp-partner.google.com \
    --cc=hskinnemoen@google.com \
    --cc=jasowang@redhat.com \
    --cc=kfting@nuvoton.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=titusr@google.com \
    --cc=venture@google.com \
    --cc=wuhaotsh@google.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).