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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390daf4480sm183236735e9.27.2025.02.10.06.50.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 06:50:04 -0800 (PST) Message-ID: Date: Mon, 10 Feb 2025 15:50:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 13/17] hw/misc: Support NPCM8XX CLK Module Registers To: Hao Wu , peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, chli30@nuvoton.corp-partner.google.com, pbonzini@redhat.com, jasowang@redhat.com, alistair@alistair23.me References: <20250206221203.4187217-1-wuhaotsh@google.com> <20250206221203.4187217-14-wuhaotsh@google.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250206221203.4187217-14-wuhaotsh@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/25 23:11, Hao Wu wrote: > NPCM8XX adds a few new registers and have a different set of reset > values to the CLK modules. This patch supports them. > > This patch doesn't support the new clock values generated by these > registers. Currently no modules use these new clock values so they > are not necessary at this point. > Implementation of these clocks might be required when implementing > these modules. > > Reviewed-by: Titus Rwantare > Reviewed-by: Peter Maydell > Signed-off-by: Hao Wu > --- > hw/misc/npcm_clk.c | 113 +++++++++++++++++++++++++++++++++++-- > include/hw/misc/npcm_clk.h | 10 +++- > 2 files changed, 117 insertions(+), 6 deletions(-) > diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h > index f47614ac8d..8fa1e14bdd 100644 > --- a/include/hw/misc/npcm_clk.h > +++ b/include/hw/misc/npcm_clk.h > @@ -1,5 +1,5 @@ > /* > - * Nuvoton NPCM7xx Clock Control Registers. > + * Nuvoton NPCM7xx/8xx Clock Control Registers. > * > * Copyright 2020 Google LLC > * > @@ -21,11 +21,12 @@ > #include "hw/sysbus.h" > > #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) > +#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t)) > /* > * Number of maximum registers in NPCM device state structure. Don't change > * this without incrementing the version_id in the vmstate. > */ > -#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS > +#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS This also breaks vmstate_npcm_clk migration.