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References: <20180807075757.7242-1-joel@jms.id.au>
	<20180807075757.7242-6-joel@jms.id.au>
From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>
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Date: Tue, 7 Aug 2018 12:29:15 +0200
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Subject: Re: [Qemu-devel] [PATCH 5/7] aspeed_sdmc: Handle ECC training
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To: Joel Stanley <joel@jms.id.au>, Peter Maydell <peter.maydell@linaro.org>
Cc: Andrew Jeffery <andrew@aj.id.au>, qemu-arm@nongnu.org, qemu-devel@nongnu.org

On 08/07/2018 09:57 AM, Joel Stanley wrote:
> This is required to ensure u-boot SDRAM training completes.
>=20
> Signed-off-by: Joel Stanley <joel@jms.id.au>



Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>

Thanks,

C.

> ---
>  hw/misc/aspeed_sdmc.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>=20
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index 522e01ef8c0d..89de3138aff0 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -27,6 +27,10 @@
>  #define R_STATUS1         (0x60 / 4)
>  #define   PHY_BUSY_STATE      BIT(0)
> =20
> +#define R_ECC_TEST_CTRL   (0x70 / 4)
> +#define   ECC_TEST_FINISHED   BIT(12)
> +#define   ECC_TEST_FAIL       BIT(13)
> +
>  /*
>   * Configuration register Ox4 (for Aspeed AST2400 SOC)
>   *
> @@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr=
 addr, uint64_t data,
>              /* Will never return 'busy' */
>              data &=3D ~PHY_BUSY_STATE;
>              break;
> +        case R_ECC_TEST_CTRL:
> +            /* Always done, always happy */
> +            data |=3D ECC_TEST_FINISHED;
> +            data &=3D ~ECC_TEST_FAIL;
> +            break;
>          default:
>              break;
>          }
>=20