From: BALATON Zoltan <balaton@eik.bme.hu>
To: qemu-devel@nongnu.org
Cc: Gerd Hoffmann <kraxel@redhat.com>,
marcandre.lureau@redhat.com, philmd@linaro.org
Subject: Re: [PATCH] ati-vga: Separate default control bit for source
Date: Wed, 29 Oct 2025 14:39:04 +0100 (CET) [thread overview]
Message-ID: <c4d5feac-3ae8-ae30-ad01-5c65e46bc60f@eik.bme.hu> (raw)
In-Reply-To: <f34373a4-d8a7-4993-b41c-052c76d9e5e1@eik.bme.hu>
On Thu, 23 Oct 2025, BALATON Zoltan wrote:
> On Tue, 7 Oct 2025, BALATON Zoltan wrote:
>> The DP_GUI_MASTER_CNTL register has separate bits for src and dest but
>> we were only looking at the dest bit. Use the correct bit for source.
>
> Ping?
Ping^2
Is there anybody sending a pull request with this and other ati-vga patch
before the freeze?
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/display/ati_2d.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
>> index 309bb5ccb6..e69b15b570 100644
>> --- a/hw/display/ati_2d.c
>> +++ b/hw/display/ati_2d.c
>> @@ -43,7 +43,8 @@ static int ati_bpp_from_datatype(ATIVGAState *s)
>> }
>> }
>>
>> -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl &
>> GMC_DST_PITCH_OFFSET_CNTL)
>> +#define DFLT_CNTL_SRC (s->regs.dp_gui_master_cntl &
>> GMC_SRC_PITCH_OFFSET_CNTL)
>> +#define DFLT_CNTL_DST (s->regs.dp_gui_master_cntl &
>> GMC_DST_PITCH_OFFSET_CNTL)
>>
>> void ati_2d_blt(ATIVGAState *s)
>> {
>> @@ -63,12 +64,12 @@ void ati_2d_blt(ATIVGAState *s)
>> qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
>> return;
>> }
>> - int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch :
>> s->regs.default_pitch;
>> + int dst_stride = DFLT_CNTL_DST ? s->regs.dst_pitch :
>> s->regs.default_pitch;
>> if (!dst_stride) {
>> qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
>> return;
>> }
>> - uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
>> + uint8_t *dst_bits = s->vga.vram_ptr + (DFLT_CNTL_DST ?
>> s->regs.dst_offset : s->regs.default_offset);
>>
>> if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
>> @@ -97,13 +98,13 @@ void ati_2d_blt(ATIVGAState *s)
>> s->regs.src_x : s->regs.src_x + 1 -
>> s->regs.dst_width);
>> unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
>> s->regs.src_y : s->regs.src_y + 1 -
>> s->regs.dst_height);
>> - int src_stride = DEFAULT_CNTL ?
>> + int src_stride = DFLT_CNTL_SRC ?
>> s->regs.src_pitch : s->regs.default_pitch;
>> if (!src_stride) {
>> qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
>> return;
>> }
>> - uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
>> + uint8_t *src_bits = s->vga.vram_ptr + (DFLT_CNTL_SRC ?
>> s->regs.src_offset : s->regs.default_offset);
>>
>> if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
>>
>
>
next prev parent reply other threads:[~2025-10-29 13:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 19:54 [PATCH] ati-vga: Separate default control bit for source BALATON Zoltan
2025-10-23 13:45 ` BALATON Zoltan
2025-10-29 13:39 ` BALATON Zoltan [this message]
2025-11-03 2:55 ` Chad Jablonski
2025-11-03 12:40 ` BALATON Zoltan
2025-11-04 19:13 ` Chad Jablonski
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