From: Richard Henderson <richard.henderson@linaro.org>
To: Christoph Muellner <christoph.muellner@vrull.eu>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jeff Law <jeffreyalaw@gmail.com>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
liweiwei@iscas.ac.cn
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [RFC PATCH v2] riscv: Add support for the Zfa extension
Date: Mon, 10 Apr 2023 18:20:01 -0700 [thread overview]
Message-ID: <c4e9dbac-cfec-ae70-436f-82f0d70b3539@linaro.org> (raw)
In-Reply-To: <20230331182824.4104580-1-christoph.muellner@vrull.eu>
On 3/31/23 11:28, Christoph Muellner wrote:
> +/*
> + * Implement float64 to int32_t conversion without saturation;
> + * the result is supplied modulo 2^32.
> + * Rounding mode is RTZ.
> + * Flag behaviour identical to fcvt.w.d (see F specification).
> + *
> + * Similar conversion of this function can be found in
> + * target/arm/vfp_helper.c (fjcvtzs): f64->i32 with other fflag behaviour, and
> + * target/alpha/fpu_helper.c (do_cvttq): f64->i64 with support for several
> + * rounding modes and different fflag behaviour.
> + */
> +uint64_t helper_fcvtmod_w_d(CPURISCVState *env, uint64_t value)
I am still of the opinion this should be moved to fpu/softfloat-parts.c.
The "other fflag" behaviour is very likely a bug in one or more of the three implementations.
r~
prev parent reply other threads:[~2023-04-11 1:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-31 18:28 [RFC PATCH v2] riscv: Add support for the Zfa extension Christoph Muellner
2023-04-10 13:23 ` LIU Zhiwei
2023-04-13 14:55 ` Christoph Müllner
2023-04-11 1:20 ` Richard Henderson [this message]
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