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[40.133.238.146]) by smtp.gmail.com with ESMTPSA id c7-20020a170902b68700b001a064282b11sm8392638pls.151.2023.04.10.18.20.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Apr 2023 18:20:04 -0700 (PDT) Message-ID: Date: Mon, 10 Apr 2023 18:20:01 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [RFC PATCH v2] riscv: Add support for the Zfa extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Jeff Law , Tsukasa OI , liweiwei@iscas.ac.cn Cc: Daniel Henrique Barboza , Liu Zhiwei References: <20230331182824.4104580-1-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230331182824.4104580-1-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -52 X-Spam_score: -5.3 X-Spam_bar: ----- X-Spam_report: (-5.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.246, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/31/23 11:28, Christoph Muellner wrote: > +/* > + * Implement float64 to int32_t conversion without saturation; > + * the result is supplied modulo 2^32. > + * Rounding mode is RTZ. > + * Flag behaviour identical to fcvt.w.d (see F specification). > + * > + * Similar conversion of this function can be found in > + * target/arm/vfp_helper.c (fjcvtzs): f64->i32 with other fflag behaviour, and > + * target/alpha/fpu_helper.c (do_cvttq): f64->i64 with support for several > + * rounding modes and different fflag behaviour. > + */ > +uint64_t helper_fcvtmod_w_d(CPURISCVState *env, uint64_t value) I am still of the opinion this should be moved to fpu/softfloat-parts.c. The "other fflag" behaviour is very likely a bug in one or more of the three implementations. r~