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21 Jan 2025 17:44:12 -0800 X-CSE-ConnectionGUID: s1BcAjG+TN+z2GsJnBsN3g== X-CSE-MsgGUID: DfIsWDbVQkWRD+PbjKmTeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,223,1732608000"; d="scan'208";a="107590215" Received: from xiaoyaol-hp-g830.ccr.corp.intel.com (HELO [10.124.247.1]) ([10.124.247.1]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2025 17:44:09 -0800 Message-ID: Date: Wed, 22 Jan 2025 09:44:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] target/i386: Introduce SierraForest-v2 model To: Tao Su , qemu-devel@nongnu.org Cc: pbonzini@redhat.com, imammedo@redhat.com, zhao1.liu@linux.intel.com, xuelian.guo@intel.com References: <20250121020650.1899618-1-tao1.su@linux.intel.com> <20250121020650.1899618-2-tao1.su@linux.intel.com> Content-Language: en-US From: Xiaoyao Li In-Reply-To: <20250121020650.1899618-2-tao1.su@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=192.198.163.14; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -63 X-Spam_score: -6.4 X-Spam_bar: ------ X-Spam_report: (-6.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.996, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/21/2025 10:06 AM, Tao Su wrote: > Update SierraForest CPU model to add LAM, 4 bits indicating certain bits > of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl, > bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri, > movdir64b) > > Also add GDS-NO and RFDS-NO to indicate the related vulnerabilities are > mitigated in stepping 3. > > Tested-by: Xuelian Guo > Signed-off-by: Tao Su Reviewed-by: Xiaoyao Li > --- > target/i386/cpu.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 1b9c11022c..6db8d6c9ba 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -4549,6 +4549,25 @@ static const X86CPUDefinition builtin_x86_defs[] = { > .model_id = "Intel Xeon Processor (SierraForest)", > .versions = (X86CPUVersionDefinition[]) { > { .version = 1 }, > + { > + .version = 2, > + .props = (PropValue[]) { > + { "ss", "on" }, > + { "tsc-adjust", "on" }, > + { "cldemote", "on" }, > + { "movdiri", "on" }, > + { "movdir64b", "on" }, > + { "gds-no", "on" }, > + { "rfds-no", "on" }, > + { "lam", "on" }, > + { "intel-psfd", "on"}, > + { "ipred-ctrl", "on"}, > + { "rrsba-ctrl", "on"}, > + { "bhi-ctrl", "on"}, > + { "stepping", "3" }, > + { /* end of list */ } > + } > + }, > { /* end of list */ }, > }, > },