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Mon, 20 Sep 2021 07:23:48 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id cp17sm13347666pjb.3.2021.09.20.07.23.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Sep 2021 07:23:47 -0700 (PDT) Subject: Re: [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file To: WANG Xuerui , qemu-devel@nongnu.org References: <20210920080451.408655-1-git@xen0n.name> <20210920080451.408655-4-git@xen0n.name> From: Richard Henderson Message-ID: Date: Mon, 20 Sep 2021 07:23:46 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210920080451.408655-4-git@xen0n.name> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/20/21 1:04 AM, WANG Xuerui wrote: > Signed-off-by: WANG Xuerui > --- > tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 183 insertions(+) > create mode 100644 tcg/loongarch/tcg-target.h > > diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h > new file mode 100644 > index 0000000000..b5e70e01b5 > --- /dev/null > +++ b/tcg/loongarch/tcg-target.h > @@ -0,0 +1,183 @@ > +/* > + * Tiny Code Generator for QEMU > + * > + * Copyright (c) 2021 WANG Xuerui > + * > + * Based on tcg/riscv/tcg-target.h > + * > + * Copyright (c) 2018 SiFive, Inc You may have copied too much from the riscv port? :-) > +/* > + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain > + * for the initial upstreaming of this architecture, so don't bother and just > + * support the LP64 ABI for now. > + */ > +#if defined(__loongarch64) > +# define TCG_TARGET_REG_BITS 64 > +#else > +# error unsupported LoongArch bitness s/bitness/register size/ > +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 Hmm. I was about to say this is more copying from riscv, and should be X, but now I see that this is no longer used. You can omit it now; I'll remove the other instances myself. > +/* optional instructions */ > +#define TCG_TARGET_HAS_movcond_i32 0 > +#define TCG_TARGET_HAS_div_i32 1 > +#define TCG_TARGET_HAS_rem_i32 1 > +#define TCG_TARGET_HAS_div2_i32 0 > +#define TCG_TARGET_HAS_rot_i32 1 > +#define TCG_TARGET_HAS_deposit_i32 1 > +#define TCG_TARGET_HAS_extract_i32 1 > +#define TCG_TARGET_HAS_sextract_i32 0 > +#define TCG_TARGET_HAS_extract2_i32 0 > +#define TCG_TARGET_HAS_add2_i32 0 > +#define TCG_TARGET_HAS_sub2_i32 0 > +#define TCG_TARGET_HAS_mulu2_i32 0 > +#define TCG_TARGET_HAS_muls2_i32 0 > +#define TCG_TARGET_HAS_muluh_i32 1 > +#define TCG_TARGET_HAS_mulsh_i32 1 > +#define TCG_TARGET_HAS_ext8s_i32 1 > +#define TCG_TARGET_HAS_ext16s_i32 1 > +#define TCG_TARGET_HAS_ext8u_i32 1 > +#define TCG_TARGET_HAS_ext16u_i32 1 > +#define TCG_TARGET_HAS_bswap16_i32 0 > +#define TCG_TARGET_HAS_bswap32_i32 1 > +#define TCG_TARGET_HAS_not_i32 1 > +#define TCG_TARGET_HAS_neg_i32 1 > +#define TCG_TARGET_HAS_andc_i32 1 > +#define TCG_TARGET_HAS_orc_i32 1 > +#define TCG_TARGET_HAS_eqv_i32 0 > +#define TCG_TARGET_HAS_nand_i32 0 > +#define TCG_TARGET_HAS_nor_i32 1 > +#define TCG_TARGET_HAS_clz_i32 1 > +#define TCG_TARGET_HAS_ctz_i32 1 > +#define TCG_TARGET_HAS_ctpop_i32 0 > +#define TCG_TARGET_HAS_direct_jump 0 > +#define TCG_TARGET_HAS_brcond2 0 > +#define TCG_TARGET_HAS_setcond2 0 > +#define TCG_TARGET_HAS_qemu_st8_i32 0 > + > +#if TCG_TARGET_REG_BITS == 64 You don't need this conditional, since you've asserted it at the top (and unlike riscv, have no plans to add support for riscv32 at some future point).