* [PULL v2 00/53] tcg patch queue
@ 2023-05-11 10:49 Richard Henderson
2023-05-11 10:49 ` [PULL v2 08/53] disas: Move disas.c into the target-independent source set Richard Henderson
2023-05-11 12:28 ` [PULL v2 00/53] tcg patch queue Richard Henderson
0 siblings, 2 replies; 3+ messages in thread
From: Richard Henderson @ 2023-05-11 10:49 UTC (permalink / raw)
To: qemu-devel
v2: Remove poisoned symbol CONFIG_RISCV_DIS from disas.c.
Wasn't visible from x86 with gcc or clang;
was visible from macos clang;
was visible from native riscv clang.
r~
The following changes since commit fff86d48a2cdcdfa75f845cac3e0d3cdd848d9e4:
Merge tag 'migration-20230509-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-05-11 05:55:12 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230511-2
for you to fetch changes up to 335dfd253fc242b009a1b9b5d4fffbf4ea52928d:
target/loongarch: Do not include tcg-ldst.h (2023-05-11 09:53:41 +0100)
----------------------------------------------------------------
target/m68k: Fix gen_load_fp regression
accel/tcg: Ensure fairness with icount
disas: Move disas.c into the target-independent source sets
tcg: Use common routines for calling slow path helpers
tcg/*: Cleanups to qemu_ld/st constraints
tcg: Remove TARGET_ALIGNED_ONLY
accel/tcg: Reorg system mode load/store helpers
----------------------------------------------------------------
Jamie Iles (2):
cpu: expose qemu_cpu_list_lock for lock-guard use
accel/tcg/tcg-accel-ops-rr: ensure fairness with icount
Richard Henderson (49):
target/m68k: Fix gen_load_fp for OS_LONG
accel/tcg: Fix atomic_mmu_lookup for reads
disas: Fix tabs and braces in disas.c
disas: Move disas.c to disas/
disas: Remove target_ulong from the interface
disas: Remove target-specific headers
tcg/i386: Introduce prepare_host_addr
tcg/i386: Use indexed addressing for softmmu fast path
tcg/aarch64: Introduce prepare_host_addr
tcg/arm: Introduce prepare_host_addr
tcg/loongarch64: Introduce prepare_host_addr
tcg/mips: Introduce prepare_host_addr
tcg/ppc: Introduce prepare_host_addr
tcg/riscv: Introduce prepare_host_addr
tcg/s390x: Introduce prepare_host_addr
tcg: Add routines for calling slow-path helpers
tcg/i386: Convert tcg_out_qemu_ld_slow_path
tcg/i386: Convert tcg_out_qemu_st_slow_path
tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path
tcg/loongarch64: Simplify constraints on qemu_ld/st
tcg/mips: Remove MO_BSWAP handling
tcg/mips: Reorg tlb load within prepare_host_addr
tcg/mips: Simplify constraints on qemu_ld/st
tcg/ppc: Reorg tcg_out_tlb_read
tcg/ppc: Adjust constraints on qemu_ld/st
tcg/ppc: Remove unused constraints A, B, C, D
tcg/ppc: Remove unused constraint J
tcg/riscv: Simplify constraints on qemu_ld/st
tcg/s390x: Use ALGFR in constructing softmmu host address
tcg/s390x: Simplify constraints on qemu_ld/st
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
target/mips: Add missing default_tcg_memop_mask
target/mips: Use MO_ALIGN instead of 0
target/mips: Remove TARGET_ALIGNED_ONLY
target/nios2: Remove TARGET_ALIGNED_ONLY
target/sh4: Use MO_ALIGN where required
target/sh4: Remove TARGET_ALIGNED_ONLY
tcg: Remove TARGET_ALIGNED_ONLY
accel/tcg: Add cpu_in_serial_context
accel/tcg: Introduce tlb_read_idx
accel/tcg: Reorg system mode load helpers
accel/tcg: Reorg system mode store helpers
target/loongarch: Do not include tcg-ldst.h
Thomas Huth (2):
disas: Move softmmu specific code to separate file
disas: Move disas.c into the target-independent source set
configs/targets/mips-linux-user.mak | 1 -
configs/targets/mips-softmmu.mak | 1 -
configs/targets/mips64-linux-user.mak | 1 -
configs/targets/mips64-softmmu.mak | 1 -
configs/targets/mips64el-linux-user.mak | 1 -
configs/targets/mips64el-softmmu.mak | 1 -
configs/targets/mipsel-linux-user.mak | 1 -
configs/targets/mipsel-softmmu.mak | 1 -
configs/targets/mipsn32-linux-user.mak | 1 -
configs/targets/mipsn32el-linux-user.mak | 1 -
configs/targets/nios2-softmmu.mak | 1 -
configs/targets/sh4-linux-user.mak | 1 -
configs/targets/sh4-softmmu.mak | 1 -
configs/targets/sh4eb-linux-user.mak | 1 -
configs/targets/sh4eb-softmmu.mak | 1 -
meson.build | 3 -
accel/tcg/internal.h | 9 +
accel/tcg/tcg-accel-ops-icount.h | 3 +-
disas/disas-internal.h | 21 +
include/disas/disas.h | 23 +-
include/exec/cpu-common.h | 1 +
include/exec/cpu-defs.h | 7 +-
include/exec/cpu_ldst.h | 26 +-
include/exec/memop.h | 13 +-
include/exec/poison.h | 1 -
tcg/loongarch64/tcg-target-con-set.h | 2 -
tcg/loongarch64/tcg-target-con-str.h | 1 -
tcg/mips/tcg-target-con-set.h | 13 +-
tcg/mips/tcg-target-con-str.h | 2 -
tcg/mips/tcg-target.h | 4 +-
tcg/ppc/tcg-target-con-set.h | 11 +-
tcg/ppc/tcg-target-con-str.h | 7 -
tcg/riscv/tcg-target-con-set.h | 2 -
tcg/riscv/tcg-target-con-str.h | 1 -
tcg/s390x/tcg-target-con-set.h | 2 -
tcg/s390x/tcg-target-con-str.h | 1 -
accel/tcg/cpu-exec-common.c | 3 +
accel/tcg/cputlb.c | 1113 ++++++++++++++++-------------
accel/tcg/tb-maint.c | 2 +-
accel/tcg/tcg-accel-ops-icount.c | 21 +-
accel/tcg/tcg-accel-ops-rr.c | 37 +-
bsd-user/elfload.c | 5 +-
cpus-common.c | 2 +-
disas/disas-mon.c | 65 ++
disas.c => disas/disas.c | 111 +--
linux-user/elfload.c | 18 +-
migration/dirtyrate.c | 26 +-
replay/replay.c | 3 +-
target/loongarch/csr_helper.c | 1 -
target/loongarch/iocsr_helper.c | 1 -
target/m68k/translate.c | 1 +
target/mips/tcg/mxu_translate.c | 3 +-
target/nios2/translate.c | 10 +
target/sh4/translate.c | 102 ++-
tcg/tcg.c | 480 ++++++++++++-
trace/control-target.c | 9 +-
target/mips/tcg/micromips_translate.c.inc | 24 +-
target/mips/tcg/mips16e_translate.c.inc | 18 +-
target/mips/tcg/nanomips_translate.c.inc | 32 +-
tcg/aarch64/tcg-target.c.inc | 347 ++++-----
tcg/arm/tcg-target.c.inc | 455 +++++-------
tcg/i386/tcg-target.c.inc | 453 +++++-------
tcg/loongarch64/tcg-target.c.inc | 313 +++-----
tcg/mips/tcg-target.c.inc | 870 +++++++---------------
tcg/ppc/tcg-target.c.inc | 512 ++++++-------
tcg/riscv/tcg-target.c.inc | 304 ++++----
tcg/s390x/tcg-target.c.inc | 314 ++++----
disas/meson.build | 6 +-
68 files changed, 2789 insertions(+), 3040 deletions(-)
create mode 100644 disas/disas-internal.h
create mode 100644 disas/disas-mon.c
rename disas.c => disas/disas.c (78%)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PULL v2 08/53] disas: Move disas.c into the target-independent source set
2023-05-11 10:49 [PULL v2 00/53] tcg patch queue Richard Henderson
@ 2023-05-11 10:49 ` Richard Henderson
2023-05-11 12:28 ` [PULL v2 00/53] tcg patch queue Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2023-05-11 10:49 UTC (permalink / raw)
To: qemu-devel; +Cc: Thomas Huth
From: Thomas Huth <thuth@redhat.com>
Use target_words_bigendian() instead of an ifdef.
Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is
a poisoned identifier, and anyway will always be set by meson.build
when building on a riscv host.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
[rth: Type change done in a separate patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/disas.c | 12 ++++++------
disas/meson.build | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/disas/disas.c b/disas/disas.c
index 45614af02d..0d2d06c2ec 100644
--- a/disas/disas.c
+++ b/disas/disas.c
@@ -122,11 +122,11 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
s->cpu = cpu;
s->info.read_memory_func = target_read_memory;
s->info.print_address_func = print_address;
-#if TARGET_BIG_ENDIAN
- s->info.endian = BFD_ENDIAN_BIG;
-#else
- s->info.endian = BFD_ENDIAN_LITTLE;
-#endif
+ if (target_words_bigendian()) {
+ s->info.endian = BFD_ENDIAN_BIG;
+ } else {
+ s->info.endian = BFD_ENDIAN_LITTLE;
+ }
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->disas_set_info) {
@@ -164,7 +164,7 @@ static void initialize_debug_host(CPUDebug *s)
# ifdef _ARCH_PPC64
s->info.cap_mode = CS_MODE_64;
# endif
-#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
+#elif defined(__riscv)
#if defined(_ILP32) || (__riscv_xlen == 32)
s->info.print_insn = print_insn_riscv32;
#elif defined(_LP64)
diff --git a/disas/meson.build b/disas/meson.build
index f40230c58f..832727e4b3 100644
--- a/disas/meson.build
+++ b/disas/meson.build
@@ -11,6 +11,7 @@ common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
+common_ss.add(files('disas.c'))
softmmu_ss.add(files('disas-mon.c'))
-specific_ss.add(files('disas.c'), capstone)
+specific_ss.add(capstone)
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PULL v2 00/53] tcg patch queue
2023-05-11 10:49 [PULL v2 00/53] tcg patch queue Richard Henderson
2023-05-11 10:49 ` [PULL v2 08/53] disas: Move disas.c into the target-independent source set Richard Henderson
@ 2023-05-11 12:28 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2023-05-11 12:28 UTC (permalink / raw)
To: qemu-devel
On 5/11/23 11:49, Richard Henderson wrote:
> v2: Remove poisoned symbol CONFIG_RISCV_DIS from disas.c.
> Wasn't visible from x86 with gcc or clang;
> was visible from macos clang;
> was visible from native riscv clang.
>
>
> r~
>
>
> The following changes since commit fff86d48a2cdcdfa75f845cac3e0d3cdd848d9e4:
>
> Merge tag 'migration-20230509-pull-request' ofhttps://gitlab.com/juan.quintela/qemu into staging (2023-05-11 05:55:12 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230511-2
>
> for you to fetch changes up to 335dfd253fc242b009a1b9b5d4fffbf4ea52928d:
>
> target/loongarch: Do not include tcg-ldst.h (2023-05-11 09:53:41 +0100)
>
> ----------------------------------------------------------------
> target/m68k: Fix gen_load_fp regression
> accel/tcg: Ensure fairness with icount
> disas: Move disas.c into the target-independent source sets
> tcg: Use common routines for calling slow path helpers
> tcg/*: Cleanups to qemu_ld/st constraints
> tcg: Remove TARGET_ALIGNED_ONLY
> accel/tcg: Reorg system mode load/store helpers
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
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