* [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common
@ 2025-04-24 22:20 Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
` (20 more replies)
0 siblings, 21 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Since v4:
- Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan)
- Use GPtrArray for get_valid_cpu_type (Richard)
- Define InterfaceInfo[] arrays (Richard)
- Collect R-b tags
Since v3:
- QAPI structure renamed as QemuTargetInfo
- MachineClass::get_valid_cpu_types() runtime
- target_aarch64() checking SysEmuTarget value
- Remove CONFIG_TCG #ifdef'ry in hw/arm/
Since v2:
- More comments from Pierrick addressed
- Use GList to register valid CPUs list
- Remove all TARGET_AARCH64 uses in hw/arm/
Since v1:
- Dropped unrelated / irrelevant patches
- Addressed Pierrick comments
- Added R-b tag
- Only considering machines, not CPUs.
Available here, based on my pending patch queue:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v5
Philippe Mathieu-Daudé (21):
qapi: Rename TargetInfo structure as QemuTargetInfo
qemu: Convert target_name() to TargetInfo API
system/vl: Filter machine list available for a particular target
binary
hw/core/null-machine: Define machine as generic QOM type
hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces
hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine
hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro
hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
meson: Prepare to accept per-binary TargetInfo structure
implementation
config/target: Implement per-binary TargetInfo structure (ARM,
AARCH64)
hw/arm/aspeed: Build objects once
hw/arm/raspi: Build objects once
hw/core/machine: Allow dynamic registration of valid CPU types
hw/arm/virt: Register valid CPU types dynamically
hw/arm/virt: Check accelerator availability at runtime
qemu/target_info: Add %target_arch field to TargetInfo
qemu/target_info: Add target_aarch64() helper
hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
hw/core: Introduce MachineClass::get_default_cpu_type() helper
hw/arm/virt: Get default CPU type at runtime
MAINTAINERS | 8 ++++
meson.build | 11 +++++
qapi/machine.json | 10 ++---
include/hw/arm/machines-qom.h | 31 +++++++++++++
include/hw/boards.h | 16 ++++++-
include/hw/core/cpu.h | 2 -
include/qemu/target-info-impl.h | 31 +++++++++++++
include/qemu/target-info.h | 34 ++++++++++++++
configs/targets/aarch64-softmmu.c | 23 ++++++++++
configs/targets/arm-softmmu.c | 23 ++++++++++
cpu-target.c | 5 ---
hw/arm/aspeed.c | 31 ++++++++++---
hw/arm/b-l475e-iot01a.c | 2 +
hw/arm/bananapi_m2u.c | 3 +-
hw/arm/bcm2836.c | 4 --
hw/arm/collie.c | 2 +
hw/arm/cubieboard.c | 3 +-
hw/arm/digic_boards.c | 3 +-
hw/arm/exynos4_boards.c | 3 ++
hw/arm/fby35.c | 2 +
hw/arm/highbank.c | 3 ++
hw/arm/imx25_pdk.c | 3 +-
hw/arm/imx8mp-evk.c | 4 +-
hw/arm/integratorcp.c | 3 +-
hw/arm/kzm.c | 3 +-
hw/arm/mcimx6ul-evk.c | 4 +-
hw/arm/mcimx7d-sabre.c | 4 +-
hw/arm/microbit.c | 2 +
hw/arm/mps2-tz.c | 5 +++
hw/arm/mps2.c | 5 +++
hw/arm/mps3r.c | 2 +
hw/arm/msf2-som.c | 3 +-
hw/arm/musca.c | 3 ++
hw/arm/musicpal.c | 3 +-
hw/arm/netduino2.c | 3 +-
hw/arm/netduinoplus2.c | 3 +-
hw/arm/npcm7xx_boards.c | 6 +++
hw/arm/npcm8xx_boards.c | 2 +
hw/arm/olimex-stm32-h405.c | 3 +-
hw/arm/omap_sx1.c | 3 ++
hw/arm/orangepi.c | 3 +-
hw/arm/raspi.c | 10 +++--
hw/arm/raspi4b.c | 2 +
hw/arm/realview.c | 5 +++
hw/arm/sabrelite.c | 3 +-
hw/arm/sbsa-ref.c | 2 +
hw/arm/stellaris.c | 3 ++
hw/arm/stm32vldiscovery.c | 3 +-
hw/arm/versatilepb.c | 3 ++
hw/arm/vexpress.c | 3 ++
hw/arm/virt.c | 74 ++++++++++++++++++-------------
hw/arm/xilinx_zynq.c | 2 +
hw/arm/xlnx-versal-virt.c | 2 +
hw/arm/xlnx-zcu102.c | 2 +
hw/core/machine-qmp-cmds.c | 5 ++-
hw/core/machine.c | 36 +++++++++++++++
hw/core/null-machine.c | 20 ++++++++-
plugins/loader.c | 2 +-
system/vl.c | 7 +--
target-info-qom.c | 24 ++++++++++
target-info-stub.c | 22 +++++++++
target-info.c | 26 +++++++++++
target/arm/machine.c | 12 +++++
configs/targets/meson.build | 5 +++
hw/arm/meson.build | 12 +++--
65 files changed, 513 insertions(+), 89 deletions(-)
create mode 100644 include/hw/arm/machines-qom.h
create mode 100644 include/qemu/target-info-impl.h
create mode 100644 include/qemu/target-info.h
create mode 100644 configs/targets/aarch64-softmmu.c
create mode 100644 configs/targets/arm-softmmu.c
create mode 100644 target-info-qom.c
create mode 100644 target-info-stub.c
create mode 100644 target-info.c
create mode 100644 configs/targets/meson.build
--
2.47.1
^ permalink raw reply [flat|nested] 47+ messages in thread
* [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé
` (19 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé,
Markus Armbruster
The QAPI-generated 'TargetInfo' structure name is only used
in a single file. We want to heavily use another structure
similarly named. Rename the QAPI one, since structure names
are not part of the public API.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20250422145502.70770-2-philmd@linaro.org>
---
qapi/machine.json | 10 +++++-----
hw/core/machine-qmp-cmds.c | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index a9ff8076317..c8feb9fe17b 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -275,15 +275,15 @@
{ 'command': 'query-current-machine', 'returns': 'CurrentMachineParams' }
##
-# @TargetInfo:
+# @QemuTargetInfo:
#
-# Information describing the QEMU target.
+# Information on the target configuration built into the QEMU binary.
#
# @arch: the target architecture
#
# Since: 1.2
##
-{ 'struct': 'TargetInfo',
+{ 'struct': 'QemuTargetInfo',
'data': { 'arch': 'SysEmuTarget' } }
##
@@ -291,11 +291,11 @@
#
# Return information about the target for this QEMU
#
-# Returns: TargetInfo
+# Returns: QemuTargetInfo
#
# Since: 1.2
##
-{ 'command': 'query-target', 'returns': 'TargetInfo' }
+{ 'command': 'query-target', 'returns': 'QemuTargetInfo' }
##
# @UuidInfo:
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 9447e345b3c..a5e635152dc 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -134,9 +134,9 @@ CurrentMachineParams *qmp_query_current_machine(Error **errp)
return params;
}
-TargetInfo *qmp_query_target(Error **errp)
+QemuTargetInfo *qmp_query_target(Error **errp)
{
- TargetInfo *info = g_malloc0(sizeof(*info));
+ QemuTargetInfo *info = g_malloc0(sizeof(*info));
info->arch = qapi_enum_parse(&SysEmuTarget_lookup, target_name(), -1,
&error_abort);
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
` (18 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Have target_name() be a target-agnostic method, dispatching
to a per-target TargetInfo singleton structure.
By default a stub singleton is used. No logical change
expected.
Inspired-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
MAINTAINERS | 7 +++++++
meson.build | 3 +++
include/hw/core/cpu.h | 2 --
include/qemu/target-info-impl.h | 26 ++++++++++++++++++++++++++
include/qemu/target-info.h | 19 +++++++++++++++++++
cpu-target.c | 5 -----
hw/core/machine-qmp-cmds.c | 1 +
plugins/loader.c | 2 +-
system/vl.c | 2 +-
target-info-stub.c | 19 +++++++++++++++++++
target-info.c | 16 ++++++++++++++++
11 files changed, 93 insertions(+), 9 deletions(-)
create mode 100644 include/qemu/target-info-impl.h
create mode 100644 include/qemu/target-info.h
create mode 100644 target-info-stub.c
create mode 100644 target-info.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d82d962f1a4..451e2778888 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1926,6 +1926,13 @@ F: tests/functional/test_empty_cpu_model.py
F: tests/unit/test-smp-parse.c
T: git https://gitlab.com/ehabkost/qemu.git machine-next
+TargetInfo API
+M: Pierrick Bouvier <pierrick.bouvier@linaro.org>
+M: Philippe Mathieu-Daudé <philmd@linaro.org>
+S: Supported
+F: include/qemu/target-info*.h
+F: target-info*.c
+
Xtensa Machines
---------------
sim
diff --git a/meson.build b/meson.build
index c736a6f4c4b..8ae70dbe45a 100644
--- a/meson.build
+++ b/meson.build
@@ -3795,6 +3795,9 @@ endif
common_ss.add(pagevary)
specific_ss.add(files('page-target.c', 'page-vary-target.c'))
+common_ss.add(files('target-info.c'))
+specific_ss.add(files('target-info-stub.c'))
+
subdir('backends')
subdir('disas')
subdir('migration')
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 5b645df59f5..9d9448341d1 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1115,8 +1115,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
void cpu_exec_reset_hold(CPUState *cpu);
-const char *target_name(void);
-
#ifdef COMPILING_PER_TARGET
extern const VMStateDescription vmstate_cpu_common;
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
new file mode 100644
index 00000000000..d30805f7f28
--- /dev/null
+++ b/include/qemu/target-info-impl.h
@@ -0,0 +1,26 @@
+/*
+ * QEMU TargetInfo structure definition
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef QEMU_TARGET_INFO_IMPL_H
+#define QEMU_TARGET_INFO_IMPL_H
+
+#include "qemu/target-info.h"
+
+typedef struct TargetInfo {
+ /* runtime equivalent of TARGET_NAME definition */
+ const char *target_name;
+} TargetInfo;
+
+/**
+ * target_info:
+ *
+ * Returns: The TargetInfo structure definition for this target binary.
+ */
+const TargetInfo *target_info(void);
+
+#endif
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
new file mode 100644
index 00000000000..1007dc9a5e4
--- /dev/null
+++ b/include/qemu/target-info.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU target info API
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef QEMU_TARGET_INFO_H
+#define QEMU_TARGET_INFO_H
+
+/**
+ * target_name:
+ *
+ * Returns: Canonical target name (i.e. "i386").
+ */
+const char *target_name(void);
+
+#endif
diff --git a/cpu-target.c b/cpu-target.c
index c99d208a7c4..3f82d3ea444 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -165,8 +165,3 @@ bool target_words_bigendian(void)
{
return TARGET_BIG_ENDIAN;
}
-
-const char *target_name(void)
-{
- return TARGET_NAME;
-}
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index a5e635152dc..d82043e1c68 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -19,6 +19,7 @@
#include "qapi/qobject-input-visitor.h"
#include "qapi/type-helpers.h"
#include "qemu/uuid.h"
+#include "qemu/target-info.h"
#include "qom/qom-qobject.h"
#include "system/hostmem.h"
#include "system/hw_accel.h"
diff --git a/plugins/loader.c b/plugins/loader.c
index 0d6e082e170..8f0d75c9049 100644
--- a/plugins/loader.c
+++ b/plugins/loader.c
@@ -29,7 +29,7 @@
#include "qemu/xxhash.h"
#include "qemu/plugin.h"
#include "qemu/memalign.h"
-#include "hw/core/cpu.h"
+#include "qemu/target-info.h"
#include "exec/tb-flush.h"
#include "plugin.h"
diff --git a/system/vl.c b/system/vl.c
index c17945c4939..cdf6eb9ee49 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -40,6 +40,7 @@
#include "qemu/help_option.h"
#include "qemu/hw-version.h"
#include "qemu/uuid.h"
+#include "qemu/target-info.h"
#include "system/reset.h"
#include "system/runstate.h"
#include "system/runstate-action.h"
@@ -79,7 +80,6 @@
#include "hw/block/block.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
-#include "hw/core/cpu.h"
#include "migration/cpr.h"
#include "migration/misc.h"
#include "migration/snapshot.h"
diff --git a/target-info-stub.c b/target-info-stub.c
new file mode 100644
index 00000000000..076b9254dd0
--- /dev/null
+++ b/target-info-stub.c
@@ -0,0 +1,19 @@
+/*
+ * QEMU target info stubs
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+
+static const TargetInfo target_info_stub = {
+ .target_name = TARGET_NAME,
+};
+
+const TargetInfo *target_info(void)
+{
+ return &target_info_stub;
+}
diff --git a/target-info.c b/target-info.c
new file mode 100644
index 00000000000..84b18931e7e
--- /dev/null
+++ b/target-info.c
@@ -0,0 +1,16 @@
+/*
+ * QEMU target info helpers
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info.h"
+#include "qemu/target-info-impl.h"
+
+const char *target_name(void)
+{
+ return target_info()->target_name;
+}
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
` (17 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Binaries can register a QOM type to filter their machines
by filling their TargetInfo::machine_typename field.
This can be used by example by main() -> machine_help_func()
to filter the machines list.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/target-info-impl.h | 2 ++
include/qemu/target-info.h | 8 ++++++++
system/vl.c | 3 ++-
target-info-stub.c | 2 ++
target-info.c | 5 +++++
5 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index d30805f7f28..d0e8c86176c 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -14,6 +14,8 @@
typedef struct TargetInfo {
/* runtime equivalent of TARGET_NAME definition */
const char *target_name;
+ /* QOM typename machines for this binary must implement */
+ const char *machine_typename;
} TargetInfo;
/**
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 1007dc9a5e4..0224b35b166 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -16,4 +16,12 @@
*/
const char *target_name(void);
+/**
+ * target_machine_typename:
+ *
+ * Returns: Name of the QOM interface implemented by machines
+ * usable on this target binary.
+ */
+const char *target_machine_typename(void);
+
#endif
diff --git a/system/vl.c b/system/vl.c
index cdf6eb9ee49..e8706a9ce87 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -27,6 +27,7 @@
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/module.h"
+#include "qemu/target-info.h"
#include "exec/cpu-common.h"
#include "exec/page-vary.h"
#include "hw/qdev-properties.h"
@@ -1564,7 +1565,7 @@ static void machine_help_func(const QDict *qdict)
GSList *el;
const char *type = qdict_get_try_str(qdict, "type");
- machines = object_class_get_list(TYPE_MACHINE, false);
+ machines = object_class_get_list(target_machine_typename(), false);
if (type) {
ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines));
if (machine_class) {
diff --git a/target-info-stub.c b/target-info-stub.c
index 076b9254dd0..218e5898e7f 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -8,9 +8,11 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
+#include "hw/boards.h"
static const TargetInfo target_info_stub = {
.target_name = TARGET_NAME,
+ .machine_typename = TYPE_MACHINE,
};
const TargetInfo *target_info(void)
diff --git a/target-info.c b/target-info.c
index 84b18931e7e..0042769e3a2 100644
--- a/target-info.c
+++ b/target-info.c
@@ -14,3 +14,8 @@ const char *target_name(void)
{
return target_info()->target_name;
}
+
+const char *target_machine_typename(void)
+{
+ return target_info()->machine_typename;
+}
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:30 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
` (16 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
While DEFINE_MACHINE() is a succinct macro, it doesn't
allow registering QOM interfaces to the defined machine.
Convert to the generic DEFINE_TYPES() in preparation to
register interfaces.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/core/null-machine.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index a6e477a2d88..3e03771d570 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -42,8 +42,10 @@ static void machine_none_init(MachineState *mch)
}
}
-static void machine_none_machine_init(MachineClass *mc)
+static void null_machine_class_init(ObjectClass *oc, const void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "empty machine";
mc->init = machine_none_init;
mc->max_cpus = 1;
@@ -55,4 +57,12 @@ static void machine_none_machine_init(MachineClass *mc)
mc->no_cdrom = 1;
}
-DEFINE_MACHINE("none", machine_none_machine_init)
+static const TypeInfo null_machine_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("none"),
+ .parent = TYPE_MACHINE,
+ .class_init = null_machine_class_init,
+ },
+};
+
+DEFINE_TYPES(null_machine_types)
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
` (15 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE
QOM interface names to allow machines to implement them.
Register these interfaces in common code in target_info-qom.c used
by all binaries because QOM interfaces must be registered before
being checked (see next commit with the 'none' machine).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 1 +
include/hw/arm/machines-qom.h | 18 ++++++++++++++++++
target-info-qom.c | 24 ++++++++++++++++++++++++
3 files changed, 43 insertions(+)
create mode 100644 include/hw/arm/machines-qom.h
create mode 100644 target-info-qom.c
diff --git a/meson.build b/meson.build
index 8ae70dbe45a..32e6aeb295d 100644
--- a/meson.build
+++ b/meson.build
@@ -3796,6 +3796,7 @@ common_ss.add(pagevary)
specific_ss.add(files('page-target.c', 'page-vary-target.c'))
common_ss.add(files('target-info.c'))
+system_ss.add(files('target-info-qom.c'))
specific_ss.add(files('target-info-stub.c'))
subdir('backends')
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
new file mode 100644
index 00000000000..a17225f5f92
--- /dev/null
+++ b/include/hw/arm/machines-qom.h
@@ -0,0 +1,18 @@
+/*
+ * QOM type definitions for ARM / Aarch64 machines
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_ARM_MACHINES_QOM_H
+#define HW_ARM_MACHINES_QOM_H
+
+#define TYPE_TARGET_ARM_MACHINE \
+ "target-info-arm-machine"
+
+#define TYPE_TARGET_AARCH64_MACHINE \
+ "target-info-aarch64-machine"
+
+#endif
diff --git a/target-info-qom.c b/target-info-qom.c
new file mode 100644
index 00000000000..7fd58d24818
--- /dev/null
+++ b/target-info-qom.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU binary/target API (QOM types)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qom/object.h"
+#include "hw/arm/machines-qom.h"
+
+static const TypeInfo target_info_types[] = {
+ {
+ .name = TYPE_TARGET_ARM_MACHINE,
+ .parent = TYPE_INTERFACE,
+ },
+ {
+ .name = TYPE_TARGET_AARCH64_MACHINE,
+ .parent = TYPE_INTERFACE,
+ },
+};
+
+DEFINE_TYPES(target_info_types)
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
` (14 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
When we'll start to use target_machine_typename() to filter
machines for the ARM/Aarch64 binaries, the 'none' machine
would be filtered out. Register the proper interfaces to keep
it available.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/core/null-machine.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 3e03771d570..9009d3d96f5 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,6 +16,7 @@
#include "hw/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
+#include "hw/arm/machines-qom.h"
static void machine_none_init(MachineState *mch)
{
@@ -62,6 +63,11 @@ static const TypeInfo null_machine_types[] = {
.name = MACHINE_TYPE_NAME("none"),
.parent = TYPE_MACHINE,
.class_init = null_machine_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { TYPE_TARGET_ARM_MACHINE },
+ { },
+ },
},
};
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:44 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
` (13 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
DEFINE_MACHINE_WITH_INTERFACES() is similar to DEFINE_MACHINE()
but allows to pass a InterfaceInfo[] pointer.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/boards.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 765dc8dd35e..3573907d597 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -744,7 +744,7 @@ struct MachineState {
} \
} while (0)
-#define DEFINE_MACHINE(namestr, machine_initfn) \
+#define DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces) \
static void machine_initfn##_class_init(ObjectClass *oc, const void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
@@ -754,6 +754,7 @@ struct MachineState {
.name = MACHINE_TYPE_NAME(namestr), \
.parent = TYPE_MACHINE, \
.class_init = machine_initfn##_class_init, \
+ .interfaces = ifaces, \
}; \
static void machine_initfn##_register_types(void) \
{ \
@@ -761,6 +762,9 @@ struct MachineState {
} \
type_init(machine_initfn##_register_types)
+#define DEFINE_MACHINE(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, NULL)
+
extern GlobalProperty hw_compat_10_0[];
extern const size_t hw_compat_10_0_len;
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
@ 2025-04-24 22:20 ` Philippe Mathieu-Daudé
2025-04-24 22:35 ` Pierrick Bouvier
2025-04-25 0:16 ` BALATON Zoltan
2025-04-24 22:21 ` [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
` (12 subsequent siblings)
20 siblings, 2 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:20 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
will be available on qemu-system-arm and qemu-system-aarch64
binaries.
One defined with DEFINE_MACHINE_AARCH64() will only be available
in the qemu-system-aarch64 binary.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/machines-qom.h | 13 +++++++++++++
target/arm/machine.c | 12 ++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index a17225f5f92..6277ee986d9 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -9,10 +9,23 @@
#ifndef HW_ARM_MACHINES_QOM_H
#define HW_ARM_MACHINES_QOM_H
+#include "hw/boards.h"
+
#define TYPE_TARGET_ARM_MACHINE \
"target-info-arm-machine"
#define TYPE_TARGET_AARCH64_MACHINE \
"target-info-aarch64-machine"
+extern InterfaceInfo arm_aarch64_machine_interfaces[];
+extern InterfaceInfo aarch64_machine_interfaces[];
+
+#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
+ arm_aarch64_machine_interfaces)
+
+#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
+ DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
+ aarch64_machine_interfaces)
+
#endif
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 978249fb71b..193c7a9cff0 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -8,6 +8,7 @@
#include "cpu-features.h"
#include "migration/cpu.h"
#include "target/arm/gtimer.h"
+#include "hw/arm/machines-qom.h"
static bool vfp_needed(void *opaque)
{
@@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
+
+InterfaceInfo arm_aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_ARM_MACHINE },
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { }
+};
+
+InterfaceInfo aarch64_machine_interfaces[] = {
+ { TYPE_TARGET_AARCH64_MACHINE },
+ { }
+};
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
` (11 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Register machines to be able to run with the qemu-system-arm
and qemu-system-aarch64 binaries, except few machines which
are only available on the qemu-system-aarch64 binary:
$ git grep TARGET_AARCH64 hw/arm/meson.build
hw/arm/meson.build:31:arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
hw/arm/meson.build:50:arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
$ git grep -W AARCH64 hw/arm/Kconfig
hw/arm/Kconfig=185=config SBSA_REF
hw/arm/Kconfig-186- bool
hw/arm/Kconfig-187- default y
hw/arm/Kconfig:188: depends on TCG && AARCH64
--
hw/arm/Kconfig=413=config XLNX_ZYNQMP_ARM
hw/arm/Kconfig-414- bool
hw/arm/Kconfig-415- default y if PIXMAN
hw/arm/Kconfig:416: depends on TCG && AARCH64
--
hw/arm/Kconfig=435=config XLNX_VERSAL
hw/arm/Kconfig-436- bool
hw/arm/Kconfig-437- default y
hw/arm/Kconfig:438: depends on TCG && AARCH64
--
hw/arm/Kconfig=475=config NPCM8XX
hw/arm/Kconfig-476- bool
hw/arm/Kconfig-477- default y
hw/arm/Kconfig:478: depends on TCG && AARCH64
--
hw/arm/Kconfig=605=config FSL_IMX8MP_EVK
hw/arm/Kconfig-606- bool
hw/arm/Kconfig-607- default y
hw/arm/Kconfig:608: depends on TCG && AARCH64
$ git grep -wW TARGET_AARCH64 hw/arm | fgrep -4 MACHINE_TYPE_NAME
...
hw/arm/aspeed.c:1939:#ifdef TARGET_AARCH64
hw/arm/aspeed.c-1940- }, {
hw/arm/aspeed.c-1941- .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
hw/arm/aspeed.c-1949- .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
hw/arm/raspi.c:420:#ifdef TARGET_AARCH64
hw/arm/raspi.c-421- }, {
hw/arm/raspi.c-422- .name = MACHINE_TYPE_NAME("raspi3ap"),
hw/arm/raspi.c-429- }, {
hw/arm/raspi.c-430- .name = MACHINE_TYPE_NAME("raspi3b"),
This can be verified as:
$ diff -u0 <(qemu-system-arm -M help) <(qemu-system-aarch64 -M help)
@@ -5,3 +4,0 @@
-ast2700-evb Aspeed AST2700 A0 EVB (Cortex-A35) (alias of ast2700a0-evb)
-ast2700a0-evb Aspeed AST2700 A0 EVB (Cortex-A35)
-ast2700a1-evb Aspeed AST2700 A1 EVB (Cortex-A35)
@@ -22 +18,0 @@
-imx8mp-evk NXP i.MX 8M Plus EVK Board
@@ -49 +44,0 @@
-npcm845-evb Nuvoton NPCM845 Evaluation Board (Cortex-A35)
@@ -63,3 +57,0 @@
-raspi3ap Raspberry Pi 3A+ (revision 1.0)
-raspi3b Raspberry Pi 3B (revision 1.2)
-raspi4b Raspberry Pi 4B (revision 1.5)
@@ -72 +63,0 @@
-sbsa-ref QEMU 'SBSA Reference' ARM Virtual Machine
@@ -116,2 +106,0 @@
-xlnx-versal-virt Xilinx Versal Virtual development board
-xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on the value of smp
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/arm/aspeed.c | 25 ++++++++++++++++++++++++-
hw/arm/b-l475e-iot01a.c | 2 ++
hw/arm/bananapi_m2u.c | 3 ++-
hw/arm/collie.c | 2 ++
hw/arm/cubieboard.c | 3 ++-
hw/arm/digic_boards.c | 3 ++-
hw/arm/exynos4_boards.c | 3 +++
hw/arm/fby35.c | 2 ++
hw/arm/highbank.c | 3 +++
hw/arm/imx25_pdk.c | 3 ++-
hw/arm/imx8mp-evk.c | 4 +++-
hw/arm/integratorcp.c | 3 ++-
hw/arm/kzm.c | 3 ++-
hw/arm/mcimx6ul-evk.c | 4 +++-
hw/arm/mcimx7d-sabre.c | 4 +++-
hw/arm/microbit.c | 2 ++
hw/arm/mps2-tz.c | 5 +++++
hw/arm/mps2.c | 5 +++++
hw/arm/mps3r.c | 2 ++
hw/arm/msf2-som.c | 3 ++-
hw/arm/musca.c | 3 +++
hw/arm/musicpal.c | 3 ++-
hw/arm/netduino2.c | 3 ++-
hw/arm/netduinoplus2.c | 3 ++-
hw/arm/npcm7xx_boards.c | 6 ++++++
hw/arm/npcm8xx_boards.c | 2 ++
hw/arm/olimex-stm32-h405.c | 3 ++-
hw/arm/omap_sx1.c | 3 +++
hw/arm/orangepi.c | 3 ++-
hw/arm/raspi.c | 6 ++++++
hw/arm/raspi4b.c | 2 ++
hw/arm/realview.c | 5 +++++
hw/arm/sabrelite.c | 3 ++-
hw/arm/sbsa-ref.c | 2 ++
hw/arm/stellaris.c | 3 +++
hw/arm/stm32vldiscovery.c | 3 ++-
hw/arm/versatilepb.c | 3 +++
hw/arm/vexpress.c | 3 +++
hw/arm/virt.c | 2 ++
hw/arm/xilinx_zynq.c | 2 ++
hw/arm/xlnx-versal-virt.c | 2 ++
hw/arm/xlnx-zcu102.c | 2 ++
42 files changed, 133 insertions(+), 18 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 20f418fb63b..06a49343d4a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -15,6 +15,7 @@
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_eeprom.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
@@ -1773,91 +1774,113 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_palmetto_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast2500-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2500_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("romulus-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_romulus_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_sonorapass_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_witherspoon_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_yosemitev2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("tiogapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_tiogapass_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("g220a-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_g220a_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_firework_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fp5280g2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_quanta_q71l_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fuji_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("bletchley-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_bletchley_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("fby35-bmc"),
.parent = MACHINE_TYPE_NAME("ast2600-evb"),
.class_init = aspeed_machine_fby35_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a0_evb_class_init,
- }, {
+ .interfaces = aarch64_machine_interfaces,
+ }, {
.name = MACHINE_TYPE_NAME("ast2700a1-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
+ .interfaces = aarch64_machine_interfaces,
#endif
}, {
.name = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 34ed2e0851b..ed275ecce9d 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -29,6 +29,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/core/split-irq.h"
+#include "hw/arm/machines-qom.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/display/dm163.h"
@@ -131,6 +132,7 @@ static const TypeInfo bl475e_machine_type[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(Bl475eMachineState),
.class_init = bl475e_machine_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}
};
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index b750a575f72..90c3ec1c255 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,6 +27,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
static struct arm_boot_info bpim2u_binfo;
@@ -144,4 +145,4 @@ static void bpim2u_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("bpim2u", bpim2u_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("bpim2u-pdk", bpim2u_machine_init)
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 93bb190f1f9..ac841ef2b0a 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -15,6 +15,7 @@
#include "hw/boards.h"
#include "strongarm.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/address-spaces.h"
#include "qom/object.h"
@@ -86,6 +87,7 @@ static const TypeInfo collie_machine_typeinfo = {
.parent = TYPE_MACHINE,
.class_init = collie_machine_class_init,
.instance_size = sizeof(CollieMachineState),
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void collie_machine_register_types(void)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index d665d4edd97..c66424effa0 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,6 +22,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/i2c/i2c.h"
static struct arm_boot_info cubieboard_binfo = {
@@ -125,4 +126,4 @@ static void cubieboard_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("cubieboard", cubieboard_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("cubieboard", cubieboard_machine_init)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 466b8b84c0e..f71c16be0fe 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -29,6 +29,7 @@
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "hw/arm/digic.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/loader.h"
#include "system/qtest.h"
@@ -145,4 +146,4 @@ static void canon_a1100_machine_init(MachineClass *mc)
mc->default_ram_id = "ram";
}
-DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("canon-a1100", canon_a1100_machine_init)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 73049741312..e39a35df190 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "system/address-spaces.h"
#include "hw/arm/exynos4210.h"
#include "hw/net/lan9118.h"
@@ -172,6 +173,7 @@ static const TypeInfo nuri_type = {
.name = MACHINE_TYPE_NAME("nuri"),
.parent = TYPE_MACHINE,
.class_init = nuri_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void smdkc210_class_init(ObjectClass *oc, const void *data)
@@ -192,6 +194,7 @@ static const TypeInfo smdkc210_type = {
.name = MACHINE_TYPE_NAME("smdkc210"),
.parent = TYPE_MACHINE,
.class_init = smdkc210_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void exynos4_machines_init(void)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index e123fa69e19..7e00e8a0fc1 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -14,6 +14,7 @@
#include "hw/qdev-clock.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#define TYPE_FBY35 MACHINE_TYPE_NAME("fby35")
OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35);
@@ -187,6 +188,7 @@ static const TypeInfo fby35_types[] = {
.class_init = fby35_class_init,
.instance_size = sizeof(Fby35State),
.instance_init = fby35_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 3ae26ebebdc..1656a82190d 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/loader.h"
#include "net/net.h"
#include "system/runstate.h"
@@ -363,6 +364,7 @@ static const TypeInfo highbank_type = {
.name = MACHINE_TYPE_NAME("highbank"),
.parent = TYPE_MACHINE,
.class_init = highbank_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void midway_class_init(ObjectClass *oc, const void *data)
@@ -387,6 +389,7 @@ static const TypeInfo midway_type = {
.name = MACHINE_TYPE_NAME("midway"),
.parent = TYPE_MACHINE,
.class_init = midway_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void calxeda_machines_init(void)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index e95ea5e4e18..87d3c8b91c5 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -28,6 +28,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/fsl-imx25.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
@@ -150,4 +151,4 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("imx25-pdk", imx25_pdk_machine_init)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index b3082fa60d8..a40443fb0a7 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -10,6 +10,7 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mp.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "system/qtest.h"
@@ -100,4 +101,5 @@ static void imx8mp_evk_machine_init(MachineClass *mc)
mc->max_cpus = FSL_IMX8MP_NUM_CPUS;
mc->default_ram_id = "imx8mp-evk.ram";
}
-DEFINE_MACHINE("imx8mp-evk", imx8mp_evk_machine_init)
+
+DEFINE_MACHINE_AARCH64("imx8mp", imx8mp_evk_machine_init)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index b1d8fbd470a..9e10d0343c7 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -13,6 +13,7 @@
#include "migration/vmstate.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_integrator_debug.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
@@ -693,7 +694,7 @@ static void integratorcp_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("integratorcp", integratorcp_machine_init)
static const Property core_properties[] = {
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 362c1454099..1de68b1c5d0 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -17,6 +17,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx31.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
@@ -139,4 +140,4 @@ static void kzm_machine_init(MachineClass *mc)
mc->default_ram_id = "kzm.ram";
}
-DEFINE_MACHINE("kzm", kzm_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("kzm", kzm_machine_init)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 86982cb0772..cbc319fa737 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -76,4 +77,5 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->default_ram_id = "mcimx6ul-evk.ram";
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
+
+DEFINE_MACHINE_ARM_AARCH64("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 33119610113..349924dbb21 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -16,6 +16,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx7.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -76,4 +77,5 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
mc->default_ram_id = "mcimx7d-sabre.ram";
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)
+
+DEFINE_MACHINE_ARM_AARCH64("mcimx7d-sabre", mcimx7d_sabre_machine_init)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 525443fdb97..41db5715c3f 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -12,6 +12,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "system/system.h"
#include "system/address-spaces.h"
@@ -74,6 +75,7 @@ static const TypeInfo microbit_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(MicrobitMachineState),
.class_init = microbit_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void microbit_machine_init(void)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 5dd87cc0281..2d2637e5d4a 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -52,6 +52,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
+#include "hw/arm/machines-qom.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "system/address-spaces.h"
@@ -1463,24 +1464,28 @@ static const TypeInfo mps2tz_an505_info = {
.name = TYPE_MPS2TZ_AN505_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an505_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2tz_an521_info = {
.name = TYPE_MPS2TZ_AN521_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an521_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps3tz_an524_info = {
.name = TYPE_MPS3TZ_AN524_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an524_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps3tz_an547_info = {
.name = TYPE_MPS3TZ_AN547_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an547_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void mps2tz_machine_init(void)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 58efb41e6db..523d56908ed 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
+#include "hw/arm/machines-qom.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "system/address-spaces.h"
@@ -563,24 +564,28 @@ static const TypeInfo mps2_an385_info = {
.name = TYPE_MPS2_AN385_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an385_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an386_info = {
.name = TYPE_MPS2_AN386_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an386_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an500_info = {
.name = TYPE_MPS2_AN500_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an500_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an511_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void mps2_machine_init(void)
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 48c73acc62e..683dd97ee09 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -37,6 +37,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
+#include "hw/arm/machines-qom.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/intc/arm_gicv3.h"
@@ -634,6 +635,7 @@ static const TypeInfo mps3r_machine_types[] = {
.name = TYPE_MPS3R_AN536_MACHINE,
.parent = TYPE_MPS3R_MACHINE,
.class_init = mps3r_an536_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 29c76c68605..864b7e56aed 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -32,6 +32,7 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/qdev-clock.h"
#include "system/address-spaces.h"
#include "hw/arm/msf2-soc.h"
@@ -108,4 +109,4 @@ static void emcraft_sf2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("emcraft-sf2", emcraft_sf2_machine_init)
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 250b3b5bf84..64d4f41cd60 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -26,6 +26,7 @@
#include "system/system.h"
#include "hw/arm/boot.h"
#include "hw/arm/armsse.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/char/pl011.h"
#include "hw/core/split-irq.h"
@@ -657,12 +658,14 @@ static const TypeInfo musca_a_info = {
.name = TYPE_MUSCA_A_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_a_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo musca_b1_info = {
.name = TYPE_MUSCA_B1_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_b1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void musca_machine_init(void)
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 329b162eb20..548c218a039 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -15,6 +15,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/boards.h"
@@ -1346,7 +1347,7 @@ static void musicpal_machine_init(MachineClass *mc)
machine_add_audiodev_property(mc);
}
-DEFINE_MACHINE("musicpal", musicpal_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("musicpal", musicpal_machine_init)
static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data)
{
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index df793c77fe1..6b7fee0973f 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -30,6 +30,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (120MHz) */
#define SYSCLK_FRQ 120000000ULL
@@ -65,4 +66,4 @@ static void netduino2_machine_init(MachineClass *mc)
mc->ignore_memory_transaction_failures = true;
}
-DEFINE_MACHINE("netduino2", netduino2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("netduino2", netduino2_machine_init)
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 81b6334cf72..4a666f226b0 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -30,6 +30,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (168MHz) */
#define SYSCLK_FRQ 168000000ULL
@@ -65,4 +66,4 @@ static void netduinoplus2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("netduinoplus2", netduinoplus2_machine_init)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 465a0e5acec..2bd90847acd 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "hw/arm/npcm7xx.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
@@ -549,22 +550,27 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm750-evb"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = npcm750_evb_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gsj"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gsj_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gbs_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("kudo-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = kudo_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("mori-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = mori_bmc_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 9d9f6d0c9a6..9167f1f4099 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -19,6 +19,7 @@
#include "chardev/char.h"
#include "hw/boards.h"
#include "hw/arm/npcm8xx.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/loader.h"
#include "hw/qdev-core.h"
@@ -248,6 +249,7 @@ static const TypeInfo npcm8xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm845-evb"),
.parent = TYPE_NPCM8XX_MACHINE,
.class_init = npcm845_evb_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 1f15620f9fd..4300cfb8862 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
@@ -71,4 +72,4 @@ static void olimex_stm32_h405_machine_init(MachineClass *mc)
mc->default_ram_size = 0;
}
-DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 1d89a202bb9..d53a9aa49e9 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -32,6 +32,7 @@
#include "hw/arm/omap.h"
#include "hw/boards.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/qtest.h"
#include "system/address-spaces.h"
@@ -219,6 +220,7 @@ static const TypeInfo sx1_machine_v2_type = {
.name = MACHINE_TYPE_NAME("sx1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v2_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
@@ -238,6 +240,7 @@ static const TypeInfo sx1_machine_v1_type = {
.name = MACHINE_TYPE_NAME("sx1-v1"),
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v1_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void sx1_machine_init(void)
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e0956880d11..3ea78811069 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -26,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-h3.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
static struct arm_boot_info orangepi_binfo;
@@ -124,4 +125,4 @@ static void orangepi_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("orangepi-pc", orangepi_machine_init)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 9d9af63d654..2a6b6aac0a6 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -25,6 +25,7 @@
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
@@ -394,23 +395,28 @@ static const TypeInfo raspi_machine_types[] = {
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
#endif
}, {
.name = TYPE_RASPI_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 20082d52667..b88af07b037 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -11,6 +11,7 @@
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
+#include "hw/arm/machines-qom.h"
#include "hw/arm/raspi_platform.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/registerfields.h"
@@ -127,6 +128,7 @@ static const TypeInfo raspi4b_machine_type = {
.parent = TYPE_RASPI_BASE_MACHINE,
.instance_size = sizeof(Raspi4bMachineState),
.class_init = raspi4b_machine_class_init,
+ .interfaces = aarch64_machine_interfaces,
};
static void raspi4b_machine_register_type(void)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 5c9050490b4..9deacbd6075 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -13,6 +13,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
+#include "hw/arm/machines-qom.h"
#include "hw/core/split-irq.h"
#include "hw/net/lan9118.h"
#include "hw/net/smc91c111.h"
@@ -431,6 +432,7 @@ static const TypeInfo realview_eb_type = {
.name = MACHINE_TYPE_NAME("realview-eb"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data)
@@ -452,6 +454,7 @@ static const TypeInfo realview_eb_mpcore_type = {
.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
.parent = TYPE_MACHINE,
.class_init = realview_eb_mpcore_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_pb_a8_class_init(ObjectClass *oc, const void *data)
@@ -471,6 +474,7 @@ static const TypeInfo realview_pb_a8_type = {
.name = MACHINE_TYPE_NAME("realview-pb-a8"),
.parent = TYPE_MACHINE,
.class_init = realview_pb_a8_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data)
@@ -491,6 +495,7 @@ static const TypeInfo realview_pbx_a9_type = {
.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
.parent = TYPE_MACHINE,
.class_init = realview_pbx_a9_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void realview_machine_init(void)
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index df60d47c6fd..91c7467fdc2 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -14,6 +14,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
@@ -113,4 +114,4 @@ static void sabrelite_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("sabrelite", sabrelite_machine_init)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index deae5cf9861..907c3c948cd 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -34,6 +34,7 @@
#include "hw/arm/bsa.h"
#include "hw/arm/fdt.h"
#include "hw/arm/smmuv3.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/ide/ide-bus.h"
@@ -920,6 +921,7 @@ static const TypeInfo sbsa_ref_info = {
.instance_init = sbsa_ref_instance_init,
.class_init = sbsa_ref_class_init,
.instance_size = sizeof(SBSAMachineState),
+ .interfaces = aarch64_machine_interfaces,
};
static void sbsa_ref_machine_init(void)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 031ea3a24e7..9fea3b6e75e 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -15,6 +15,7 @@
#include "hw/sd/sd.h"
#include "hw/ssi/ssi.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
@@ -1427,6 +1428,7 @@ static const TypeInfo lm3s811evb_type = {
.name = MACHINE_TYPE_NAME("lm3s811evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s811evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
/*
@@ -1448,6 +1450,7 @@ static const TypeInfo lm3s6965evb_type = {
.name = MACHINE_TYPE_NAME("lm3s6965evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s6965evb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void stellaris_machine_init(void)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index e6c1f5b8d7d..d042bef0bd0 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
/* stm32vldiscovery implementation is derived from netduinoplus2 */
@@ -68,4 +69,4 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+DEFINE_MACHINE_ARM_AARCH64("stm32vldiscovery", stm32vldiscovery_machine_init)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 5cf1a70d10d..8f2a34f8bd9 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -12,6 +12,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
#include "system/system.h"
@@ -431,6 +432,7 @@ static const TypeInfo versatilepb_type = {
.name = MACHINE_TYPE_NAME("versatilepb"),
.parent = TYPE_MACHINE,
.class_init = versatilepb_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void versatileab_class_init(ObjectClass *oc, const void *data)
@@ -452,6 +454,7 @@ static const TypeInfo versatileab_type = {
.name = MACHINE_TYPE_NAME("versatileab"),
.parent = TYPE_MACHINE,
.class_init = versatileab_class_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void versatile_machine_init(void)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 35f8d05ea17..6faecea2635 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -27,6 +27,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
+#include "hw/arm/machines-qom.h"
#include "hw/net/lan9118.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
@@ -850,6 +851,7 @@ static const TypeInfo vexpress_a9_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a9_class_init,
.instance_init = vexpress_a9_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static const TypeInfo vexpress_a15_info = {
@@ -857,6 +859,7 @@ static const TypeInfo vexpress_a15_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a15_class_init,
.instance_init = vexpress_a15_instance_init,
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void vexpress_machine_init(void)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 177f3dd22c1..6185ac1046f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -37,6 +37,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
#include "hw/arm/virt.h"
+#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/vfio/vfio-calxeda-xgmac.h"
#include "hw/vfio/vfio-amd-xgbe.h"
@@ -123,6 +124,7 @@ static void arm_virt_compat_set(MachineClass *mc)
.name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
.parent = TYPE_VIRT_MACHINE, \
.class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
+ .interfaces = arm_aarch64_machine_interfaces, \
}; \
static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
{ \
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 0372cd0ac46..dd164e1b6a8 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -20,6 +20,7 @@
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/boards.h"
@@ -480,6 +481,7 @@ static const TypeInfo zynq_machine_type = {
.parent = TYPE_MACHINE,
.class_init = zynq_machine_class_init,
.instance_size = sizeof(ZynqMachineState),
+ .interfaces = arm_aarch64_machine_interfaces,
};
static void zynq_machine_register_types(void)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index adadbb72902..dee5cf8a3a9 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -20,6 +20,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "target/arm/multiprocessing.h"
#include "qom/object.h"
@@ -833,6 +834,7 @@ static const TypeInfo versal_virt_machine_init_typeinfo = {
.instance_init = versal_virt_machine_instance_init,
.instance_size = sizeof(VersalVirt),
.instance_finalize = versal_virt_machine_finalize,
+ .interfaces = aarch64_machine_interfaces,
};
static void versal_virt_machine_init_register_types(void)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 14b6641a713..330f375f63a 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -19,6 +19,7 @@
#include "qapi/error.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/arm/boot.h"
+#include "hw/arm/machines-qom.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
@@ -303,6 +304,7 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
.class_init = xlnx_zcu102_machine_class_init,
.instance_init = xlnx_zcu102_machine_instance_init,
.instance_size = sizeof(XlnxZCU102),
+ .interfaces = aarch64_machine_interfaces,
};
static void xlnx_zcu102_machine_init_register_types(void)
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
` (10 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
If a file defining the binary TargetInfo structure is available,
link with it. Otherwise keep using the stub.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
MAINTAINERS | 1 +
meson.build | 9 ++++++++-
configs/targets/meson.build | 4 ++++
3 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 configs/targets/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index 451e2778888..63cf1e6ed5b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1932,6 +1932,7 @@ M: Philippe Mathieu-Daudé <philmd@linaro.org>
S: Supported
F: include/qemu/target-info*.h
F: target-info*.c
+F: configs/targets/*.c
Xtensa Machines
---------------
diff --git a/meson.build b/meson.build
index 32e6aeb295d..70ee7e838ed 100644
--- a/meson.build
+++ b/meson.build
@@ -3204,6 +3204,7 @@ config_devices_mak_list = []
config_devices_h = {}
config_target_h = {}
config_target_mak = {}
+config_target_info = {}
disassemblers = {
'alpha' : ['CONFIG_ALPHA_DIS'],
@@ -3797,9 +3798,9 @@ specific_ss.add(files('page-target.c', 'page-vary-target.c'))
common_ss.add(files('target-info.c'))
system_ss.add(files('target-info-qom.c'))
-specific_ss.add(files('target-info-stub.c'))
subdir('backends')
+subdir('configs/targets')
subdir('disas')
subdir('migration')
subdir('monitor')
@@ -4260,6 +4261,12 @@ foreach target : target_dirs
arch_srcs += gdbstub_xml
endif
+ if target in config_target_info
+ arch_srcs += config_target_info[target]
+ else
+ arch_srcs += files('target-info-stub.c')
+ endif
+
t = target_arch[target_base_arch].apply(config_target, strict: false)
arch_srcs += t.sources()
arch_deps += t.dependencies()
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
new file mode 100644
index 00000000000..a9f6b24ec01
--- /dev/null
+++ b/configs/targets/meson.build
@@ -0,0 +1,4 @@
+foreach target : [
+ ]
+ config_target_info += {target : files(target + '.c')}
+endforeach
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64)
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
` (9 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Implement the TargetInfo structure for qemu-system-arm
and qemu-system-aarch64 binaries.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/aarch64-softmmu.c | 22 ++++++++++++++++++++++
configs/targets/arm-softmmu.c | 22 ++++++++++++++++++++++
configs/targets/meson.build | 1 +
3 files changed, 45 insertions(+)
create mode 100644 configs/targets/aarch64-softmmu.c
create mode 100644 configs/targets/arm-softmmu.c
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
new file mode 100644
index 00000000000..375e6fa0b7b
--- /dev/null
+++ b/configs/targets/aarch64-softmmu.c
@@ -0,0 +1,22 @@
+/*
+ * QEMU binary/target API (qemu-system-aarch64)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "hw/arm/machines-qom.h"
+#include "target/arm/cpu-qom.h"
+
+static const TargetInfo target_info_aarch64_system = {
+ .target_name = "aarch64",
+ .machine_typename = TYPE_TARGET_AARCH64_MACHINE,
+};
+
+const TargetInfo *target_info(void)
+{
+ return &target_info_aarch64_system;
+}
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
new file mode 100644
index 00000000000..d4acdae64f3
--- /dev/null
+++ b/configs/targets/arm-softmmu.c
@@ -0,0 +1,22 @@
+/*
+ * QEMU binary/target API (qemu-system-arm)
+ *
+ * Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target-info-impl.h"
+#include "hw/arm/machines-qom.h"
+#include "target/arm/cpu-qom.h"
+
+static const TargetInfo target_info_arm_system = {
+ .target_name = "arm",
+ .machine_typename = TYPE_TARGET_ARM_MACHINE,
+};
+
+const TargetInfo *target_info(void)
+{
+ return &target_info_arm_system;
+}
diff --git a/configs/targets/meson.build b/configs/targets/meson.build
index a9f6b24ec01..cca2514eb51 100644
--- a/configs/targets/meson.build
+++ b/configs/targets/meson.build
@@ -1,4 +1,5 @@
foreach target : [
+ 'arm-softmmu', 'aarch64-softmmu',
]
config_target_info += {target : files(target + '.c')}
endforeach
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 13/21] hw/arm/raspi: " Philippe Mathieu-Daudé
` (8 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Now than Aspeed machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
remove the TARGET_AARCH64 #ifdef'ry and compile the
aspeed.c file once, moving it from arm_ss[] source set
to arm_common_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/aspeed.c | 6 ------
hw/arm/meson.build | 4 ++--
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 06a49343d4a..0a5b603bc97 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -180,13 +180,11 @@ struct AspeedMachineState {
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
-#ifdef TARGET_AARCH64
/* AST2700 evb hardware value */
/* SCU HW Strap1 */
#define AST2700_EVB_HW_STRAP1 0x00000800
/* SCUIO HW Strap1 */
#define AST2700_EVB_HW_STRAP2 0x00000700
-#endif
/* Rainier hardware value: (QEMU prototype) */
#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
@@ -1675,7 +1673,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
}
-#ifdef TARGET_AARCH64
static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1727,7 +1724,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
-#endif
static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
const void *data)
@@ -1870,7 +1866,6 @@ static const TypeInfo aspeed_machine_types[] = {
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
.interfaces = arm_aarch64_machine_interfaces,
-#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("ast2700a0-evb"),
.parent = TYPE_ASPEED_MACHINE,
@@ -1881,7 +1876,6 @@ static const TypeInfo aspeed_machine_types[] = {
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
.interfaces = aarch64_machine_interfaces,
-#endif
}, {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 09b1cfe5b57..f76e7fb229f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x
arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed.c',
'aspeed_soc_common.c',
'aspeed_ast2400.c',
'aspeed_ast2600.c',
'aspeed_ast10x0.c',
+ 'aspeed_ast27x0.c',
'aspeed_eeprom.c',
'fby35.c'))
-arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 13/21] hw/arm/raspi: Build objects once
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
` (7 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Now than Raspi machines can be filtered when running a
qemu-system-arm or qemu-system-aarch64 binary, we can
remove the TARGET_AARCH64 #ifdef'ry and compile the
aspeed.c file once, moving it from arm_ss[] source set
to arm_common_ss[]. Note, we expose the TYPE_BCM2837
type to qemu-system-arm, but it is not user-creatable,
so not an issue.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/bcm2836.c | 4 ----
hw/arm/raspi.c | 4 ----
hw/arm/meson.build | 8 ++++++--
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index cd61ba15054..aaaff05624c 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, const void *data)
dc->realize = bcm2836_realize;
};
-#ifdef TARGET_AARCH64
static void bcm2837_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, const void *data)
bc->clusterid = 0x0;
dc->realize = bcm2836_realize;
};
-#endif
static const TypeInfo bcm283x_types[] = {
{
@@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
-#ifdef TARGET_AARCH64
}, {
.name = TYPE_BCM2837,
.parent = TYPE_BCM283X,
.class_init = bcm2837_class_init,
-#endif
}, {
.name = TYPE_BCM283X,
.parent = TYPE_BCM283X_BASE,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 2a6b6aac0a6..d7d2920ad75 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -368,7 +368,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, const void *data)
raspi_machine_class_init(mc, rmc->board_rev);
};
-#ifdef TARGET_AARCH64
static void raspi3ap_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -388,7 +387,6 @@ static void raspi3b_machine_class_init(ObjectClass *oc, const void *data)
rmc->board_rev = 0xa02082;
raspi_machine_class_init(mc, rmc->board_rev);
};
-#endif /* TARGET_AARCH64 */
static const TypeInfo raspi_machine_types[] = {
{
@@ -406,7 +404,6 @@ static const TypeInfo raspi_machine_types[] = {
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
.interfaces = arm_aarch64_machine_interfaces,
-#ifdef TARGET_AARCH64
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
@@ -417,7 +414,6 @@ static const TypeInfo raspi_machine_types[] = {
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
.interfaces = arm_aarch64_machine_interfaces,
-#endif
}, {
.name = TYPE_RASPI_MACHINE,
.parent = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f76e7fb229f..f52034ff6a2 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
-arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
-arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
+arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files(
+ 'bcm2836.c',
+ 'bcm2838.c',
+ 'raspi.c',
+ 'raspi4b.c',
+))
arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 13/21] hw/arm/raspi: " Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:43 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
` (6 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Add MachineClass::get_valid_cpu_types(), a helper that
returns a dynamic list of CPU types. Since the helper
takes a MachineState argument, we know the machine is
created by the time we call it.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/boards.h | 4 ++++
hw/core/machine.c | 26 ++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 3573907d597..700e4f4ccf3 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -259,6 +259,9 @@ typedef struct {
* @smbios_memory_device_size:
* Default size of memory device,
* SMBIOS 3.1.0 "7.18 Memory Device (Type 17)"
+ * @get_valid_cpu_types:
+ * Returns a list of valid CPU types for this board. May be NULL
+ * if not needed.
*/
struct MachineClass {
/*< private >*/
@@ -306,6 +309,7 @@ struct MachineClass {
bool ignore_memory_transaction_failures;
int numa_mem_align_shift;
const char * const *valid_cpu_types;
+ GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ed01798d37c..0901a92b32a 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1581,6 +1581,32 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
error_append_hint(errp, "\n");
}
+ return false;
+ }
+ } else if (mc->get_valid_cpu_types) {
+ GPtrArray *vct = mc->get_valid_cpu_types(machine);
+ bool valid = false;
+
+ for (i = 0; i < vct->len; i++) {
+ if (object_class_dynamic_cast(oc, vct->pdata[i])) {
+ valid = true;
+ break;
+ }
+ }
+
+ if (!valid) {
+ g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
+
+ error_setg(errp, "Invalid CPU model: %s", requested);
+ error_append_hint(errp, "The valid models are: ");
+ for (i = 0; i < vct->len; i++) {
+ g_autofree char *model = cpu_model_from_type(vct->pdata[i]);
+ error_append_hint(errp, "%s%s",
+ model, i + 1 == vct->len ? "\n" : ", ");
+ }
+ }
+ g_ptr_array_free(vct, true);
+ if (!valid) {
return false;
}
}
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
` (5 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Replace the static array returned as MachineClass::valid_cpu_types[]
by a runtime one generated by MachineClass::get_valid_cpu_types()
once the machine is created (its options being processed).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/virt.c | 59 ++++++++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 27 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6185ac1046f..f29f541ea93 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3126,36 +3126,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
return requested_ipa_size;
}
+static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
+{
+ GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
+
+#ifdef CONFIG_TCG
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
+#endif /* CONFIG_KVM || CONFIG_HVF */
+#endif /* TARGET_AARCH64 */
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
+
+ return vct;
+}
+
static void virt_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
- static const char * const valid_cpu_types[] = {
-#ifdef CONFIG_TCG
- ARM_CPU_TYPE_NAME("cortex-a7"),
- ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a72"),
- ARM_CPU_TYPE_NAME("cortex-a76"),
- ARM_CPU_TYPE_NAME("cortex-a710"),
- ARM_CPU_TYPE_NAME("a64fx"),
- ARM_CPU_TYPE_NAME("neoverse-n1"),
- ARM_CPU_TYPE_NAME("neoverse-v1"),
- ARM_CPU_TYPE_NAME("neoverse-n2"),
-#endif /* TARGET_AARCH64 */
-#endif /* CONFIG_TCG */
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a53"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
- ARM_CPU_TYPE_NAME("host"),
-#endif /* CONFIG_KVM || CONFIG_HVF */
-#endif /* TARGET_AARCH64 */
- ARM_CPU_TYPE_NAME("max"),
- NULL
- };
mc->init = machvirt_init;
/* Start with max_cpus set to 512, which is the maximum supported by KVM.
@@ -3183,7 +3188,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
#else
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
#endif
- mc->valid_cpu_types = valid_cpu_types;
+ mc->get_valid_cpu_types = virt_get_valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:39 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé
` (4 subsequent siblings)
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
It is not possible to call accelerator runtime helpers
when QOM types are registered, because they depend on
the parsing of the '-accel FOO' command line option,
which happens after main().
Now than get_valid_cpu_types() is called after
accelerator initializations, it is safe to call the
accelerator helpers:
main
+ configure_accelerators
+ qmp_x_exit_preconfig
+ qemu_init_board
+ machine_run_board_init
+ is_cpu_type_supported
Replace compile-time check on CONFIG_{ACCEL} by
runtime check on {accel}_enabled() helpers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/virt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f29f541ea93..13aa2f34c6c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3130,7 +3130,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
{
GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
-#ifdef CONFIG_TCG
+ if (tcg_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
#ifdef TARGET_AARCH64
@@ -3144,13 +3144,13 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
#endif /* TARGET_AARCH64 */
-#endif /* CONFIG_TCG */
+ }
#ifdef TARGET_AARCH64
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ if (kvm_enabled() || hvf_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
-#endif /* CONFIG_KVM || CONFIG_HVF */
+ }
#endif /* TARGET_AARCH64 */
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
` (3 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/target-info-impl.h | 3 +++
configs/targets/aarch64-softmmu.c | 1 +
configs/targets/arm-softmmu.c | 1 +
target-info-stub.c | 1 +
4 files changed, 6 insertions(+)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index d0e8c86176c..e5ef425f2dc 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -10,10 +10,13 @@
#define QEMU_TARGET_INFO_IMPL_H
#include "qemu/target-info.h"
+#include "qapi/qapi-types-machine.h"
typedef struct TargetInfo {
/* runtime equivalent of TARGET_NAME definition */
const char *target_name;
+ /* related to TARGET_ARCH definition */
+ SysEmuTarget target_arch;
/* QOM typename machines for this binary must implement */
const char *machine_typename;
} TargetInfo;
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 375e6fa0b7b..ff89401ea34 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -13,6 +13,7 @@
static const TargetInfo target_info_aarch64_system = {
.target_name = "aarch64",
+ .target_arch = SYS_EMU_TARGET_AARCH64,
.machine_typename = TYPE_TARGET_AARCH64_MACHINE,
};
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index d4acdae64f3..22ec9e4faa3 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -13,6 +13,7 @@
static const TargetInfo target_info_arm_system = {
.target_name = "arm",
+ .target_arch = SYS_EMU_TARGET_ARM,
.machine_typename = TYPE_TARGET_ARM_MACHINE,
};
diff --git a/target-info-stub.c b/target-info-stub.c
index 218e5898e7f..e573f5c1975 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -12,6 +12,7 @@
static const TargetInfo target_info_stub = {
.target_name = TARGET_NAME,
+ .target_arch = -1,
.machine_typename = TYPE_MACHINE,
};
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
` (2 subsequent siblings)
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Add a helper to distinct the binary is targetting
Aarch64 or not.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/qemu/target-info.h | 7 +++++++
target-info.c | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 0224b35b166..395c009baf2 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -24,4 +24,11 @@ const char *target_name(void);
*/
const char *target_machine_typename(void);
+/**
+ * target_aarch64:
+ *
+ * Returns whether the target architecture is Aarch64.
+ */
+bool target_aarch64(void);
+
#endif
diff --git a/target-info.c b/target-info.c
index 0042769e3a2..7f1758ae34f 100644
--- a/target-info.c
+++ b/target-info.c
@@ -19,3 +19,8 @@ const char *target_machine_typename(void)
{
return target_info()->machine_typename;
}
+
+bool target_aarch64(void)
+{
+ return target_info()->target_arch == SYS_EMU_TARGET_AARCH64;
+}
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_aarch64() helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
hw/arm/virt.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 13aa2f34c6c..566afa4c978 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -32,6 +32,7 @@
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/option.h"
+#include "qemu/target-info.h"
#include "monitor/qdev.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
@@ -3133,7 +3134,8 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
if (tcg_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
-#ifdef TARGET_AARCH64
+ }
+ if (tcg_enabled() && target_aarch64()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
@@ -3143,15 +3145,14 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
-#endif /* TARGET_AARCH64 */
}
-#ifdef TARGET_AARCH64
+ if (target_aarch64()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
if (kvm_enabled() || hvf_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
}
-#endif /* TARGET_AARCH64 */
+ }
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
return vct;
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
20 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
MachineClass::get_default_cpu_type() runs once the machine is
created, being able to evaluate runtime checks; it returns the
machine default CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/hw/boards.h | 6 ++++++
hw/core/machine.c | 10 ++++++++++
system/vl.c | 2 +-
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 700e4f4ccf3..cc2f81cefeb 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -25,6 +25,11 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
extern MachineState *current_machine;
+/**
+ * machine_default_cpu_type: Return the machine default CPU type.
+ * @ms: Machine state
+ */
+const char *machine_default_cpu_type(const MachineState *ms);
/**
* machine_class_default_cpu_type: Return the machine default CPU type.
* @mc: Machine class
@@ -310,6 +315,7 @@ struct MachineClass {
int numa_mem_align_shift;
const char * const *valid_cpu_types;
GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
+ const char *(*get_default_cpu_type)(const MachineState *ms);
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 0901a92b32a..ba9ddf1b1f7 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1541,6 +1541,16 @@ const char *machine_class_default_cpu_type(MachineClass *mc)
return mc->default_cpu_type;
}
+const char *machine_default_cpu_type(const MachineState *ms)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if (mc->get_default_cpu_type) {
+ return mc->get_default_cpu_type(ms);
+ }
+ return machine_class_default_cpu_type(mc);
+}
+
static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
diff --git a/system/vl.c b/system/vl.c
index e8706a9ce87..338f9d75289 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -3825,7 +3825,7 @@ void qemu_init(int argc, char **argv)
migration_object_init();
/* parse features once if machine provides default cpu_type */
- current_machine->cpu_type = machine_class_default_cpu_type(machine_class);
+ current_machine->cpu_type = machine_default_cpu_type(current_machine);
if (cpu_option) {
current_machine->cpu_type = parse_cpu_option(cpu_option);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2025-04-24 22:21 ` [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
@ 2025-04-24 22:21 ` Philippe Mathieu-Daudé
2025-04-28 3:19 ` Zhang Chen
20 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:21 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson, Philippe Mathieu-Daudé
Prefer MachineClass::get_default_cpu_type() over
MachineClass::default_cpu_type to get CPU type,
evaluating TCG availability at runtime calling
tcg_enabled().
It's worth noting that this is a behavior change:
- Previously only
./configure --disable-tcg --enable-kvm
./qemu-system-aarch64 -M virt -accel kvm
would default to 'max' and
./configure --enable-tcg --enable-kvm
./qemu-system-aarch64 -M virt -accel kvm
would default to 'cortex-a15'.
- Afterward, -accel kvm will always default to 'max'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/arm/virt.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 566afa4c978..b59cc90bd36 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3127,6 +3127,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
return requested_ipa_size;
}
+static const char *virt_get_default_cpu_type(const MachineState *ms)
+{
+ return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15")
+ : ARM_CPU_TYPE_NAME("max");
+}
+
static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
{
GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
@@ -3184,11 +3190,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
mc->minimum_page_bits = 12;
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
-#ifdef CONFIG_TCG
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-#else
- mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
-#endif
+ mc->get_default_cpu_type = virt_get_default_cpu_type;
mc->get_valid_cpu_types = virt_get_valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
--
2.47.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
@ 2025-04-24 22:30 ` Pierrick Bouvier
2025-04-24 22:47 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:30 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
> While DEFINE_MACHINE() is a succinct macro, it doesn't
> allow registering QOM interfaces to the defined machine.
> Convert to the generic DEFINE_TYPES() in preparation to
> register interfaces.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/core/null-machine.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Maybe you can integrate your other series changing existing arm machines
also, so it's easy to apply this series without the other dependency.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
@ 2025-04-24 22:35 ` Pierrick Bouvier
2025-04-24 22:45 ` Philippe Mathieu-Daudé
2025-04-25 0:16 ` BALATON Zoltan
1 sibling, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
> will be available on qemu-system-arm and qemu-system-aarch64
> binaries.
>
> One defined with DEFINE_MACHINE_AARCH64() will only be available
> in the qemu-system-aarch64 binary.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/arm/machines-qom.h | 13 +++++++++++++
> target/arm/machine.c | 12 ++++++++++++
> 2 files changed, 25 insertions(+)
>
I won't block this change as we need to move on, but I still consider we
do a bad compromise between code readability/grepability, to avoid a
code size increase of +0.0005%.
Anyway, we can always change that later when adding a second architecture.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically
2025-04-24 22:21 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
@ 2025-04-24 22:38 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:21, Philippe Mathieu-Daudé wrote:
> Replace the static array returned as MachineClass::valid_cpu_types[]
> by a runtime one generated by MachineClass::get_valid_cpu_types()
> once the machine is created (its options being processed).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/virt.c | 59 ++++++++++++++++++++++++++++-----------------------
> 1 file changed, 32 insertions(+), 27 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
@ 2025-04-24 22:39 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:21, Philippe Mathieu-Daudé wrote:
> It is not possible to call accelerator runtime helpers
> when QOM types are registered, because they depend on
> the parsing of the '-accel FOO' command line option,
> which happens after main().
>
> Now than get_valid_cpu_types() is called after
> accelerator initializations, it is safe to call the
> accelerator helpers:
>
> main
> + configure_accelerators
> + qmp_x_exit_preconfig
> + qemu_init_board
> + machine_run_board_init
> + is_cpu_type_supported
>
> Replace compile-time check on CONFIG_{ACCEL} by
> runtime check on {accel}_enabled() helpers.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> hw/arm/virt.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
@ 2025-04-24 22:43 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:21, Philippe Mathieu-Daudé wrote:
> Add MachineClass::get_valid_cpu_types(), a helper that
> returns a dynamic list of CPU types. Since the helper
> takes a MachineState argument, we know the machine is
> created by the time we call it.
>
> Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/boards.h | 4 ++++
> hw/core/machine.c | 26 ++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/include/hw/boards.h b/include/hw/boards.h
> index 3573907d597..700e4f4ccf3 100644
> --- a/include/hw/boards.h
> +++ b/include/hw/boards.h
> @@ -259,6 +259,9 @@ typedef struct {
> * @smbios_memory_device_size:
> * Default size of memory device,
> * SMBIOS 3.1.0 "7.18 Memory Device (Type 17)"
> + * @get_valid_cpu_types:
> + * Returns a list of valid CPU types for this board. May be NULL
> + * if not needed.
> */
> struct MachineClass {
> /*< private >*/
> @@ -306,6 +309,7 @@ struct MachineClass {
> bool ignore_memory_transaction_failures;
> int numa_mem_align_shift;
> const char * const *valid_cpu_types;
> + GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
> strList *allowed_dynamic_sysbus_devices;
> bool auto_enable_numa_with_memhp;
> bool auto_enable_numa_with_memdev;
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index ed01798d37c..0901a92b32a 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1581,6 +1581,32 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
> error_append_hint(errp, "\n");
> }
>
> + return false;
> + }
> + } else if (mc->get_valid_cpu_types) {
Since we'll keep both valid_cpu_types, and get_value_cpu_types, instead
of doing a full replacement, would that be possible to add an assert here?
g_assert(!mc->valid_cpu_types);
and
g_assert(!mc->get_valid_cpu_types) in branch above.
This way, we make sure only one is defined.
With that,
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
@ 2025-04-24 22:44 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
> DEFINE_MACHINE_WITH_INTERFACES() is similar to DEFINE_MACHINE()
> but allows to pass a InterfaceInfo[] pointer.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/boards.h | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-24 22:35 ` Pierrick Bouvier
@ 2025-04-24 22:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:45 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 25/4/25 00:35, Pierrick Bouvier wrote:
> On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>> will be available on qemu-system-arm and qemu-system-aarch64
>> binaries.
>>
>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>> in the qemu-system-aarch64 binary.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>> target/arm/machine.c | 12 ++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>
> I won't block this change as we need to move on, but I still consider we
> do a bad compromise between code readability/grepability, to avoid a
> code size increase of +0.0005%.
I know, I'm just trying to keep moving while keeping everybody happy
(there was no further update on your v4 comments).
> Anyway, we can always change that later when adding a second architecture.
I expect this to not change for (current) homogeneous machines.
Heterogeneous machines won't use these fixed arrays; there I
expect compound literals to be more useful.
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Thanks!
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type
2025-04-24 22:30 ` Pierrick Bouvier
@ 2025-04-24 22:47 ` Philippe Mathieu-Daudé
2025-04-24 22:49 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-24 22:47 UTC (permalink / raw)
To: Pierrick Bouvier, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 25/4/25 00:30, Pierrick Bouvier wrote:
> On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
>> While DEFINE_MACHINE() is a succinct macro, it doesn't
>> allow registering QOM interfaces to the defined machine.
>> Convert to the generic DEFINE_TYPES() in preparation to
>> register interfaces.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/core/null-machine.c | 14 ++++++++++++--
>> 1 file changed, 12 insertions(+), 2 deletions(-)
>>
>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>
> Maybe you can integrate your other series changing existing arm machines
> also, so it's easy to apply this series without the other dependency.
I discarded the other series due to Zoltan comments, and only
salvaged this single patch (the others aren't needed since this
series introduces and uses DEFINE_MACHINE_WITH_INTERFACES).
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type
2025-04-24 22:47 ` Philippe Mathieu-Daudé
@ 2025-04-24 22:49 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-24 22:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: Mark Cave-Ayland, Anton Johansson
On 4/24/25 15:47, Philippe Mathieu-Daudé wrote:
> On 25/4/25 00:30, Pierrick Bouvier wrote:
>> On 4/24/25 15:20, Philippe Mathieu-Daudé wrote:
>>> While DEFINE_MACHINE() is a succinct macro, it doesn't
>>> allow registering QOM interfaces to the defined machine.
>>> Convert to the generic DEFINE_TYPES() in preparation to
>>> register interfaces.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>> hw/core/null-machine.c | 14 ++++++++++++--
>>> 1 file changed, 12 insertions(+), 2 deletions(-)
>>>
>>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>
>> Maybe you can integrate your other series changing existing arm machines
>> also, so it's easy to apply this series without the other dependency.
>
> I discarded the other series due to Zoltan comments, and only
> salvaged this single patch (the others aren't needed since this
> series introduces and uses DEFINE_MACHINE_WITH_INTERFACES).
>
Thanks, I noticed that later while reading the rest of this series.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
2025-04-24 22:35 ` Pierrick Bouvier
@ 2025-04-25 0:16 ` BALATON Zoltan
2025-04-25 6:05 ` Pierrick Bouvier
1 sibling, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-25 0:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Pierrick Bouvier, Richard Henderson, qemu-devel, Mark Cave-Ayland,
Anton Johansson
[-- Attachment #1: Type: text/plain, Size: 2774 bytes --]
On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
> will be available on qemu-system-arm and qemu-system-aarch64
> binaries.
>
> One defined with DEFINE_MACHINE_AARCH64() will only be available
> in the qemu-system-aarch64 binary.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/arm/machines-qom.h | 13 +++++++++++++
> target/arm/machine.c | 12 ++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
> index a17225f5f92..6277ee986d9 100644
> --- a/include/hw/arm/machines-qom.h
> +++ b/include/hw/arm/machines-qom.h
> @@ -9,10 +9,23 @@
> #ifndef HW_ARM_MACHINES_QOM_H
> #define HW_ARM_MACHINES_QOM_H
>
> +#include "hw/boards.h"
> +
> #define TYPE_TARGET_ARM_MACHINE \
> "target-info-arm-machine"
>
> #define TYPE_TARGET_AARCH64_MACHINE \
> "target-info-aarch64-machine"
>
> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
> +extern InterfaceInfo aarch64_machine_interfaces[];
> +
> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
> + arm_aarch64_machine_interfaces)
> +
> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
> + aarch64_machine_interfaces)
> +
> #endif
> diff --git a/target/arm/machine.c b/target/arm/machine.c
> index 978249fb71b..193c7a9cff0 100644
> --- a/target/arm/machine.c
> +++ b/target/arm/machine.c
> @@ -8,6 +8,7 @@
> #include "cpu-features.h"
> #include "migration/cpu.h"
> #include "target/arm/gtimer.h"
> +#include "hw/arm/machines-qom.h"
>
> static bool vfp_needed(void *opaque)
> {
> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
> NULL
> }
> };
> +
> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
> + { TYPE_TARGET_ARM_MACHINE },
> + { TYPE_TARGET_AARCH64_MACHINE },
> + { }
> +};
> +
> +InterfaceInfo aarch64_machine_interfaces[] = {
> + { TYPE_TARGET_AARCH64_MACHINE },
> + { }
> +};
Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
{ TYPE_TARGET_AARCH64_MACHINE }, { })
and no more macros needed. Ideally those places that are now blown up
should use DEFINE_MACHINE too. Maybe they don't yet because the parent
type is hardcoded so we should really have
DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
and remove more bolier plate that way?
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 0:16 ` BALATON Zoltan
@ 2025-04-25 6:05 ` Pierrick Bouvier
2025-04-25 9:43 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-25 6:05 UTC (permalink / raw)
To: BALATON Zoltan, Philippe Mathieu-Daudé
Cc: Richard Henderson, qemu-devel, Mark Cave-Ayland, Anton Johansson
On 4/24/25 17:16, BALATON Zoltan wrote:
> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>> will be available on qemu-system-arm and qemu-system-aarch64
>> binaries.
>>
>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>> in the qemu-system-aarch64 binary.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>> target/arm/machine.c | 12 ++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
>> index a17225f5f92..6277ee986d9 100644
>> --- a/include/hw/arm/machines-qom.h
>> +++ b/include/hw/arm/machines-qom.h
>> @@ -9,10 +9,23 @@
>> #ifndef HW_ARM_MACHINES_QOM_H
>> #define HW_ARM_MACHINES_QOM_H
>>
>> +#include "hw/boards.h"
>> +
>> #define TYPE_TARGET_ARM_MACHINE \
>> "target-info-arm-machine"
>>
>> #define TYPE_TARGET_AARCH64_MACHINE \
>> "target-info-aarch64-machine"
>>
>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>> +extern InterfaceInfo aarch64_machine_interfaces[];
>> +
>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>> + arm_aarch64_machine_interfaces)
>> +
>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>> + aarch64_machine_interfaces)
>> +
>> #endif
>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>> index 978249fb71b..193c7a9cff0 100644
>> --- a/target/arm/machine.c
>> +++ b/target/arm/machine.c
>> @@ -8,6 +8,7 @@
>> #include "cpu-features.h"
>> #include "migration/cpu.h"
>> #include "target/arm/gtimer.h"
>> +#include "hw/arm/machines-qom.h"
>>
>> static bool vfp_needed(void *opaque)
>> {
>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>> NULL
>> }
>> };
>> +
>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>> + { TYPE_TARGET_ARM_MACHINE },
>> + { TYPE_TARGET_AARCH64_MACHINE },
>> + { }
>> +};
>> +
>> +InterfaceInfo aarch64_machine_interfaces[] = {
>> + { TYPE_TARGET_AARCH64_MACHINE },
>> + { }
>> +};
>
> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>
This was requested in v4 by Richard to remove anonymous array
duplication in .data.
> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
> { TYPE_TARGET_AARCH64_MACHINE }, { })
>
> and no more macros needed. Ideally those places that are now blown up
> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
> type is hardcoded so we should really have
>
Not sure what you mean by "no more macros needed".
arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
(defined only once), which are passed as a parameter to
DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>
> and remove more bolier plate that way?
>
Could you can share a concrete example of what you expect, with the new
macros to add, and how to use them for a given board?
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 6:05 ` Pierrick Bouvier
@ 2025-04-25 9:43 ` BALATON Zoltan
2025-04-25 20:05 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-25 9:43 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
[-- Attachment #1: Type: text/plain, Size: 3982 bytes --]
On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
> On 4/24/25 17:16, BALATON Zoltan wrote:
>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>> will be available on qemu-system-arm and qemu-system-aarch64
>>> binaries.
>>>
>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>> in the qemu-system-aarch64 binary.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>> target/arm/machine.c | 12 ++++++++++++
>>> 2 files changed, 25 insertions(+)
>>>
>>> diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
>>> index a17225f5f92..6277ee986d9 100644
>>> --- a/include/hw/arm/machines-qom.h
>>> +++ b/include/hw/arm/machines-qom.h
>>> @@ -9,10 +9,23 @@
>>> #ifndef HW_ARM_MACHINES_QOM_H
>>> #define HW_ARM_MACHINES_QOM_H
>>>
>>> +#include "hw/boards.h"
>>> +
>>> #define TYPE_TARGET_ARM_MACHINE \
>>> "target-info-arm-machine"
>>>
>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>> "target-info-aarch64-machine"
>>>
>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>> +
>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>> + arm_aarch64_machine_interfaces)
>>> +
>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>> + aarch64_machine_interfaces)
>>> +
>>> #endif
>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>> index 978249fb71b..193c7a9cff0 100644
>>> --- a/target/arm/machine.c
>>> +++ b/target/arm/machine.c
>>> @@ -8,6 +8,7 @@
>>> #include "cpu-features.h"
>>> #include "migration/cpu.h"
>>> #include "target/arm/gtimer.h"
>>> +#include "hw/arm/machines-qom.h"
>>>
>>> static bool vfp_needed(void *opaque)
>>> {
>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>> NULL
>>> }
>>> };
>>> +
>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>> + { TYPE_TARGET_ARM_MACHINE },
>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>> + { }
>>> +};
>>> +
>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>> + { }
>>> +};
>>
>> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>
>
> This was requested in v4 by Richard to remove anonymous array duplication in
> .data.
>
>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>
>> and no more macros needed. Ideally those places that are now blown up
>> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
>> type is hardcoded so we should really have
>>
>
> Not sure what you mean by "no more macros needed".
No other specialised macros needed for each machine type other than
DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I suggested
to keep DEFINE_MACHINE by making it more general so it can cover the new
uses instead of bringing back the boiler plate and losing the clarity
hinding these behind the macros.
> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
> (defined only once), which are passed as a parameter to
> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>
>> and remove more bolier plate that way?
>>
>
> Could you can share a concrete example of what you expect, with the new
> macros to add, and how to use them for a given board?
I tried to do that in this message you replied to.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 9:43 ` BALATON Zoltan
@ 2025-04-25 20:05 ` Pierrick Bouvier
2025-04-25 20:29 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-25 20:05 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On 4/25/25 02:43, BALATON Zoltan wrote:
> On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
>> On 4/24/25 17:16, BALATON Zoltan wrote:
>>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>>> will be available on qemu-system-arm and qemu-system-aarch64
>>>> binaries.
>>>>
>>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>>> in the qemu-system-aarch64 binary.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> ---
>>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>>> target/arm/machine.c | 12 ++++++++++++
>>>> 2 files changed, 25 insertions(+)
>>>>
>>>> diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
>>>> index a17225f5f92..6277ee986d9 100644
>>>> --- a/include/hw/arm/machines-qom.h
>>>> +++ b/include/hw/arm/machines-qom.h
>>>> @@ -9,10 +9,23 @@
>>>> #ifndef HW_ARM_MACHINES_QOM_H
>>>> #define HW_ARM_MACHINES_QOM_H
>>>>
>>>> +#include "hw/boards.h"
>>>> +
>>>> #define TYPE_TARGET_ARM_MACHINE \
>>>> "target-info-arm-machine"
>>>>
>>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>>> "target-info-aarch64-machine"
>>>>
>>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>>> +
>>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>> + arm_aarch64_machine_interfaces)
>>>> +
>>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>> + aarch64_machine_interfaces)
>>>> +
>>>> #endif
>>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>>> index 978249fb71b..193c7a9cff0 100644
>>>> --- a/target/arm/machine.c
>>>> +++ b/target/arm/machine.c
>>>> @@ -8,6 +8,7 @@
>>>> #include "cpu-features.h"
>>>> #include "migration/cpu.h"
>>>> #include "target/arm/gtimer.h"
>>>> +#include "hw/arm/machines-qom.h"
>>>>
>>>> static bool vfp_needed(void *opaque)
>>>> {
>>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>>> NULL
>>>> }
>>>> };
>>>> +
>>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>>> + { TYPE_TARGET_ARM_MACHINE },
>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>> + { }
>>>> +};
>>>> +
>>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>> + { }
>>>> +};
>>>
>>> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
>>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>>
>>
>> This was requested in v4 by Richard to remove anonymous array duplication in
>> .data.
>>
>>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
>>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>>
>>> and no more macros needed. Ideally those places that are now blown up
>>> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
>>> type is hardcoded so we should really have
>>>
>>
>> Not sure what you mean by "no more macros needed".
>
> No other specialised macros needed for each machine type other than
> DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I suggested
> to keep DEFINE_MACHINE by making it more general so it can cover the new
> uses instead of bringing back the boiler plate and losing the clarity
> hinding these behind the macros.
>
This is exactly what we have in this series.
Patch 7 introduces DEFINE_MACHINE_WITH_INTERFACES.
I guess Philippe chose a new name to avoid modifying all existing
DEFINE_MACHINE, and I think it's understandable, as we want those
changes to impact hw/arm only first. That said, it would be very easy to
refactor/modify later, so it's not a big deal.
This patch introduces DEFINE_MACHINE_ARM_AARCH64 and DEFINE_MACHINE_AARCH64.
Is the problem with those specialized DEFINE_MACHINE_{ARM, AARCH64}
definition?
If yes, and if you prefer an explicit
DEFINE_MACHINE_WITH_INTERFACES(..., arm_aarch64_machine_interfaces), I'm
sure Philippe would be open to make such a change to satisfy reviews.
Let's just try to decide something, and move on.
>> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
>> (defined only once), which are passed as a parameter to
>> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
>
> Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>
This macro is not used for any machine definition so far, and
DEFINE_MACHINE is the "standard" macro used, at least the one most
commonly used in the codebase. So it makes sense to simply expand the
latter.
>>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>>
>>> and remove more bolier plate that way?
>>>
>>
>> Could you can share a concrete example of what you expect, with the new
>> macros to add, and how to use them for a given board?
>
> I tried to do that in this message you replied to.
>
If you refer to "DEFINE_MACHINE_EXTENDED(name, parent, initfn,
interfaces...)", this is almost exactly what patch 7 is introducing with
DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces).
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 20:05 ` Pierrick Bouvier
@ 2025-04-25 20:29 ` BALATON Zoltan
2025-04-25 20:36 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-25 20:29 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
[-- Attachment #1: Type: text/plain, Size: 6336 bytes --]
On Fri, 25 Apr 2025, Pierrick Bouvier wrote:
> On 4/25/25 02:43, BALATON Zoltan wrote:
>> On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
>>> On 4/24/25 17:16, BALATON Zoltan wrote:
>>>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>>>> will be available on qemu-system-arm and qemu-system-aarch64
>>>>> binaries.
>>>>>
>>>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>>>> in the qemu-system-aarch64 binary.
>>>>>
>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>>> ---
>>>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>>>> target/arm/machine.c | 12 ++++++++++++
>>>>> 2 files changed, 25 insertions(+)
>>>>>
>>>>> diff --git a/include/hw/arm/machines-qom.h
>>>>> b/include/hw/arm/machines-qom.h
>>>>> index a17225f5f92..6277ee986d9 100644
>>>>> --- a/include/hw/arm/machines-qom.h
>>>>> +++ b/include/hw/arm/machines-qom.h
>>>>> @@ -9,10 +9,23 @@
>>>>> #ifndef HW_ARM_MACHINES_QOM_H
>>>>> #define HW_ARM_MACHINES_QOM_H
>>>>>
>>>>> +#include "hw/boards.h"
>>>>> +
>>>>> #define TYPE_TARGET_ARM_MACHINE \
>>>>> "target-info-arm-machine"
>>>>>
>>>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>>>> "target-info-aarch64-machine"
>>>>>
>>>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>>>> +
>>>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>> + arm_aarch64_machine_interfaces)
>>>>> +
>>>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>> + aarch64_machine_interfaces)
>>>>> +
>>>>> #endif
>>>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>>>> index 978249fb71b..193c7a9cff0 100644
>>>>> --- a/target/arm/machine.c
>>>>> +++ b/target/arm/machine.c
>>>>> @@ -8,6 +8,7 @@
>>>>> #include "cpu-features.h"
>>>>> #include "migration/cpu.h"
>>>>> #include "target/arm/gtimer.h"
>>>>> +#include "hw/arm/machines-qom.h"
>>>>>
>>>>> static bool vfp_needed(void *opaque)
>>>>> {
>>>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>>>> NULL
>>>>> }
>>>>> };
>>>>> +
>>>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>>>> + { TYPE_TARGET_ARM_MACHINE },
>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>> + { }
>>>>> +};
>>>>> +
>>>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>> + { }
>>>>> +};
>>>>
>>>> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
>>>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>>>
>>>
>>> This was requested in v4 by Richard to remove anonymous array duplication
>>> in
>>> .data.
>>>
>>>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
>>>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>>>
>>>> and no more macros needed. Ideally those places that are now blown up
>>>> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
>>>> type is hardcoded so we should really have
>>>>
>>>
>>> Not sure what you mean by "no more macros needed".
>>
>> No other specialised macros needed for each machine type other than
>> DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I suggested
>> to keep DEFINE_MACHINE by making it more general so it can cover the new
>> uses instead of bringing back the boiler plate and losing the clarity
>> hinding these behind the macros.
>>
>
> This is exactly what we have in this series.
> Patch 7 introduces DEFINE_MACHINE_WITH_INTERFACES.
> I guess Philippe chose a new name to avoid modifying all existing
> DEFINE_MACHINE, and I think it's understandable, as we want those changes to
> impact hw/arm only first. That said, it would be very easy to refactor/modify
> later, so it's not a big deal.
>
> This patch introduces DEFINE_MACHINE_ARM_AARCH64 and DEFINE_MACHINE_AARCH64.
>
> Is the problem with those specialized DEFINE_MACHINE_{ARM, AARCH64}
> definition?
> If yes, and if you prefer an explicit DEFINE_MACHINE_WITH_INTERFACES(...,
> arm_aarch64_machine_interfaces), I'm sure Philippe would be open to make such
> a change to satisfy reviews.
>
> Let's just try to decide something, and move on.
>
>>> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
>>> (defined only once), which are passed as a parameter to
>>> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
>>
>> Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>>
>
> This macro is not used for any machine definition so far, and DEFINE_MACHINE
> is the "standard" macro used, at least the one most commonly used in the
> codebase. So it makes sense to simply expand the latter.
I was referring to that as an example how a DEFINE_MACHINE_WITH_INTERFACES
should work not suggesting to use OBJECT_DEFINE_TYPE_WITH_INTERFACES.
>>>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>>>
>>>> and remove more bolier plate that way?
>>>>
>>>
>>> Could you can share a concrete example of what you expect, with the new
>>> macros to add, and how to use them for a given board?
>>
>> I tried to do that in this message you replied to.
>>
>
> If you refer to "DEFINE_MACHINE_EXTENDED(name, parent, initfn,
> interfaces...)", this is almost exactly what patch 7 is introducing with
> DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces).
The difference is that OBJECT_DEFINE_TYPE_WITH_INTERFACES takes a list of
interfaces and defines the array itself and you pass the array which is
limiting as you then need to define a lot of arrays to pass to your macro
instead of only passing the elements and let it define tha array.
I just want to see instead of
static const TypeInfo machine_types[] = {
...lots of boiler plate code here
};
something like
DEFINE_MACHINE_EXTENDED(machine1, TYPE_WHATEVER_MACHINE, {INTERFACE1}, {INTERFACE2}, {})
DEFINE_MACHINE_EXTENDED(machine2, TYPE_OTHER_MACHINE, {INTERFACE1}, {INTERFACE3}, {})
DEFINE_MACHINE_EXTENDED(machine3, TYPE_THIRD_MACHINE, {INTERFACE1}, {})
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 20:29 ` BALATON Zoltan
@ 2025-04-25 20:36 ` Pierrick Bouvier
2025-04-28 6:52 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-25 20:36 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On 4/25/25 13:29, BALATON Zoltan wrote:
> On Fri, 25 Apr 2025, Pierrick Bouvier wrote:
>> On 4/25/25 02:43, BALATON Zoltan wrote:
>>> On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
>>>> On 4/24/25 17:16, BALATON Zoltan wrote:
>>>>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>>>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>>>>> will be available on qemu-system-arm and qemu-system-aarch64
>>>>>> binaries.
>>>>>>
>>>>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>>>>> in the qemu-system-aarch64 binary.
>>>>>>
>>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>>>> ---
>>>>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>>>>> target/arm/machine.c | 12 ++++++++++++
>>>>>> 2 files changed, 25 insertions(+)
>>>>>>
>>>>>> diff --git a/include/hw/arm/machines-qom.h
>>>>>> b/include/hw/arm/machines-qom.h
>>>>>> index a17225f5f92..6277ee986d9 100644
>>>>>> --- a/include/hw/arm/machines-qom.h
>>>>>> +++ b/include/hw/arm/machines-qom.h
>>>>>> @@ -9,10 +9,23 @@
>>>>>> #ifndef HW_ARM_MACHINES_QOM_H
>>>>>> #define HW_ARM_MACHINES_QOM_H
>>>>>>
>>>>>> +#include "hw/boards.h"
>>>>>> +
>>>>>> #define TYPE_TARGET_ARM_MACHINE \
>>>>>> "target-info-arm-machine"
>>>>>>
>>>>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>>>>> "target-info-aarch64-machine"
>>>>>>
>>>>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>>>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>>>>> +
>>>>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>> + arm_aarch64_machine_interfaces)
>>>>>> +
>>>>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>> + aarch64_machine_interfaces)
>>>>>> +
>>>>>> #endif
>>>>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>>>>> index 978249fb71b..193c7a9cff0 100644
>>>>>> --- a/target/arm/machine.c
>>>>>> +++ b/target/arm/machine.c
>>>>>> @@ -8,6 +8,7 @@
>>>>>> #include "cpu-features.h"
>>>>>> #include "migration/cpu.h"
>>>>>> #include "target/arm/gtimer.h"
>>>>>> +#include "hw/arm/machines-qom.h"
>>>>>>
>>>>>> static bool vfp_needed(void *opaque)
>>>>>> {
>>>>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>>>>> NULL
>>>>>> }
>>>>>> };
>>>>>> +
>>>>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>>>>> + { TYPE_TARGET_ARM_MACHINE },
>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>> + { }
>>>>>> +};
>>>>>> +
>>>>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>> + { }
>>>>>> +};
>>>>>
>>>>> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
>>>>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>>>>
>>>>
>>>> This was requested in v4 by Richard to remove anonymous array duplication
>>>> in
>>>> .data.
>>>>
>>>>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE },
>>>>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>>>>
>>>>> and no more macros needed. Ideally those places that are now blown up
>>>>> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
>>>>> type is hardcoded so we should really have
>>>>>
>>>>
>>>> Not sure what you mean by "no more macros needed".
>>>
>>> No other specialised macros needed for each machine type other than
>>> DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I suggested
>>> to keep DEFINE_MACHINE by making it more general so it can cover the new
>>> uses instead of bringing back the boiler plate and losing the clarity
>>> hinding these behind the macros.
>>>
>>
>> This is exactly what we have in this series.
>> Patch 7 introduces DEFINE_MACHINE_WITH_INTERFACES.
>> I guess Philippe chose a new name to avoid modifying all existing
>> DEFINE_MACHINE, and I think it's understandable, as we want those changes to
>> impact hw/arm only first. That said, it would be very easy to refactor/modify
>> later, so it's not a big deal.
>>
>> This patch introduces DEFINE_MACHINE_ARM_AARCH64 and DEFINE_MACHINE_AARCH64.
>>
>> Is the problem with those specialized DEFINE_MACHINE_{ARM, AARCH64}
>> definition?
>> If yes, and if you prefer an explicit DEFINE_MACHINE_WITH_INTERFACES(...,
>> arm_aarch64_machine_interfaces), I'm sure Philippe would be open to make such
>> a change to satisfy reviews.
>>
>> Let's just try to decide something, and move on.
>>
>>>> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
>>>> (defined only once), which are passed as a parameter to
>>>> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
>>>
>>> Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>>>
>>
>> This macro is not used for any machine definition so far, and DEFINE_MACHINE
>> is the "standard" macro used, at least the one most commonly used in the
>> codebase. So it makes sense to simply expand the latter.
>
> I was referring to that as an example how a DEFINE_MACHINE_WITH_INTERFACES
> should work not suggesting to use OBJECT_DEFINE_TYPE_WITH_INTERFACES.
>
>>>>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>>>>
>>>>> and remove more bolier plate that way?
>>>>>
>>>>
>>>> Could you can share a concrete example of what you expect, with the new
>>>> macros to add, and how to use them for a given board?
>>>
>>> I tried to do that in this message you replied to.
>>>
>>
>> If you refer to "DEFINE_MACHINE_EXTENDED(name, parent, initfn,
>> interfaces...)", this is almost exactly what patch 7 is introducing with
>> DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces).
>
> The difference is that OBJECT_DEFINE_TYPE_WITH_INTERFACES takes a list of
> interfaces and defines the array itself and you pass the array which is
> limiting as you then need to define a lot of arrays to pass to your macro
> instead of only passing the elements and let it define tha array.
>
> I just want to see instead of
>
> static const TypeInfo machine_types[] = {
> ...lots of boiler plate code here
> };
>
> something like
>
> DEFINE_MACHINE_EXTENDED(machine1, TYPE_WHATEVER_MACHINE, {INTERFACE1}, {INTERFACE2}, {})
> DEFINE_MACHINE_EXTENDED(machine2, TYPE_OTHER_MACHINE, {INTERFACE1}, {INTERFACE3}, {})
> DEFINE_MACHINE_EXTENDED(machine3, TYPE_THIRD_MACHINE, {INTERFACE1}, {})
>
Ok, I understand better.
It was my point as well on v4, that introducing those symbols is less
readable and less scalable, for a negligible benefit in terms of code
size, which was the primary concern.
We can always reconsider this later, especially when adding another
architecture to single binary, it's not a problem and something set in
stone.
Would you be ok if we proceed with the current version, knowing those
limitations, for now?
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
@ 2025-04-28 3:19 ` Zhang Chen
0 siblings, 0 replies; 47+ messages in thread
From: Zhang Chen @ 2025-04-28 3:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Pierrick Bouvier, Richard Henderson, qemu-devel, Mark Cave-Ayland,
Anton Johansson
On Fri, Apr 25, 2025 at 6:23 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Prefer MachineClass::get_default_cpu_type() over
> MachineClass::default_cpu_type to get CPU type,
> evaluating TCG availability at runtime calling
> tcg_enabled().
>
> It's worth noting that this is a behavior change:
>
> - Previously only
>
> ./configure --disable-tcg --enable-kvm
> ./qemu-system-aarch64 -M virt -accel kvm
>
> would default to 'max' and
>
> ./configure --enable-tcg --enable-kvm
> ./qemu-system-aarch64 -M virt -accel kvm
>
> would default to 'cortex-a15'.
>
> - Afterward, -accel kvm will always default to 'max'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhang Chen <zhangckid@gmail.com>
Thanks
Chen
> ---
> hw/arm/virt.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 566afa4c978..b59cc90bd36 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -3127,6 +3127,12 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
> return requested_ipa_size;
> }
>
> +static const char *virt_get_default_cpu_type(const MachineState *ms)
> +{
> + return tcg_enabled() ? ARM_CPU_TYPE_NAME("cortex-a15")
> + : ARM_CPU_TYPE_NAME("max");
> +}
> +
> static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
> {
> GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
> @@ -3184,11 +3190,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
> mc->minimum_page_bits = 12;
> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
> -#ifdef CONFIG_TCG
> - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> -#else
> - mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
> -#endif
> + mc->get_default_cpu_type = virt_get_default_cpu_type;
> mc->get_valid_cpu_types = virt_get_valid_cpu_types;
> mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
> mc->kvm_type = virt_kvm_type;
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-25 20:36 ` Pierrick Bouvier
@ 2025-04-28 6:52 ` Philippe Mathieu-Daudé
2025-04-28 10:31 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-28 6:52 UTC (permalink / raw)
To: Richard Henderson, Pierrick Bouvier, BALATON Zoltan
Cc: qemu-devel, Mark Cave-Ayland, Anton Johansson
On 25/4/25 22:36, Pierrick Bouvier wrote:
> On 4/25/25 13:29, BALATON Zoltan wrote:
>> On Fri, 25 Apr 2025, Pierrick Bouvier wrote:
>>> On 4/25/25 02:43, BALATON Zoltan wrote:
>>>> On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
>>>>> On 4/24/25 17:16, BALATON Zoltan wrote:
>>>>>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>>>>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>>>>>> will be available on qemu-system-arm and qemu-system-aarch64
>>>>>>> binaries.
>>>>>>>
>>>>>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>>>>>> in the qemu-system-aarch64 binary.
>>>>>>>
>>>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>>>>> ---
>>>>>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>>>>>> target/arm/machine.c | 12 ++++++++++++
>>>>>>> 2 files changed, 25 insertions(+)
>>>>>>>
>>>>>>> diff --git a/include/hw/arm/machines-qom.h
>>>>>>> b/include/hw/arm/machines-qom.h
>>>>>>> index a17225f5f92..6277ee986d9 100644
>>>>>>> --- a/include/hw/arm/machines-qom.h
>>>>>>> +++ b/include/hw/arm/machines-qom.h
>>>>>>> @@ -9,10 +9,23 @@
>>>>>>> #ifndef HW_ARM_MACHINES_QOM_H
>>>>>>> #define HW_ARM_MACHINES_QOM_H
>>>>>>>
>>>>>>> +#include "hw/boards.h"
>>>>>>> +
>>>>>>> #define TYPE_TARGET_ARM_MACHINE \
>>>>>>> "target-info-arm-machine"
>>>>>>>
>>>>>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>>>>>> "target-info-aarch64-machine"
>>>>>>>
>>>>>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>>>>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>>>>>> +
>>>>>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>>> +
>>>>>>> arm_aarch64_machine_interfaces)
>>>>>>> +
>>>>>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>>> + aarch64_machine_interfaces)
>>>>>>> +
>>>>>>> #endif
>>>>>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>>>>>> index 978249fb71b..193c7a9cff0 100644
>>>>>>> --- a/target/arm/machine.c
>>>>>>> +++ b/target/arm/machine.c
>>>>>>> @@ -8,6 +8,7 @@
>>>>>>> #include "cpu-features.h"
>>>>>>> #include "migration/cpu.h"
>>>>>>> #include "target/arm/gtimer.h"
>>>>>>> +#include "hw/arm/machines-qom.h"
>>>>>>>
>>>>>>> static bool vfp_needed(void *opaque)
>>>>>>> {
>>>>>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>>>>>> NULL
>>>>>>> }
>>>>>>> };
>>>>>>> +
>>>>>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>>>>>> + { TYPE_TARGET_ARM_MACHINE },
>>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>>> + { }
>>>>>>> +};
>>>>>>> +
>>>>>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>>> + { }
>>>>>>> +};
>>>>>>
>>>>>> Why do you need these? If you define
>>>>>> DEFINE_MACHINE_WITH_INTERFACES as
>>>>>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>>>>>
>>>>>
>>>>> This was requested in v4 by Richard to remove anonymous array
>>>>> duplication
>>>>> in
>>>>> .data.
>>>>>
>>>>>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn,
>>>>>> { TYPE_TARGET_ARM_MACHINE },
>>>>>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>>>>>
>>>>>> and no more macros needed. Ideally those places that are now blown up
>>>>>> should use DEFINE_MACHINE too. Maybe they don't yet because the
>>>>>> parent
>>>>>> type is hardcoded so we should really have
>>>>>>
>>>>>
>>>>> Not sure what you mean by "no more macros needed".
>>>>
>>>> No other specialised macros needed for each machine type other than
>>>> DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I
>>>> suggested
>>>> to keep DEFINE_MACHINE by making it more general so it can cover the
>>>> new
>>>> uses instead of bringing back the boiler plate and losing the clarity
>>>> hinding these behind the macros.
>>>>
>>>
>>> This is exactly what we have in this series.
>>> Patch 7 introduces DEFINE_MACHINE_WITH_INTERFACES.
>>> I guess Philippe chose a new name to avoid modifying all existing
>>> DEFINE_MACHINE, and I think it's understandable, as we want those
>>> changes to
>>> impact hw/arm only first. That said, it would be very easy to
>>> refactor/modify
>>> later, so it's not a big deal.
>>>
>>> This patch introduces DEFINE_MACHINE_ARM_AARCH64 and
>>> DEFINE_MACHINE_AARCH64.
>>>
>>> Is the problem with those specialized DEFINE_MACHINE_{ARM, AARCH64}
>>> definition?
>>> If yes, and if you prefer an explicit
>>> DEFINE_MACHINE_WITH_INTERFACES(...,
>>> arm_aarch64_machine_interfaces), I'm sure Philippe would be open to
>>> make such
>>> a change to satisfy reviews.
>>>
>>> Let's just try to decide something, and move on.
>>>
>>>>> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are
>>>>> arrays
>>>>> (defined only once), which are passed as a parameter to
>>>>> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
>>>>
>>>> Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>>>>
>>>
>>> This macro is not used for any machine definition so far, and
>>> DEFINE_MACHINE
>>> is the "standard" macro used, at least the one most commonly used in the
>>> codebase. So it makes sense to simply expand the latter.
>>
>> I was referring to that as an example how a
>> DEFINE_MACHINE_WITH_INTERFACES
>> should work not suggesting to use OBJECT_DEFINE_TYPE_WITH_INTERFACES.
>>
>>>>>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>>>>>
>>>>>> and remove more bolier plate that way?
>>>>>>
>>>>>
>>>>> Could you can share a concrete example of what you expect, with the
>>>>> new
>>>>> macros to add, and how to use them for a given board?
>>>>
>>>> I tried to do that in this message you replied to.
>>>>
>>>
>>> If you refer to "DEFINE_MACHINE_EXTENDED(name, parent, initfn,
>>> interfaces...)", this is almost exactly what patch 7 is introducing with
>>> DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces).
>>
>> The difference is that OBJECT_DEFINE_TYPE_WITH_INTERFACES takes a list of
>> interfaces and defines the array itself and you pass the array which is
>> limiting as you then need to define a lot of arrays to pass to your macro
>> instead of only passing the elements and let it define tha array.
>>
>> I just want to see instead of
>>
>> static const TypeInfo machine_types[] = {
>> ...lots of boiler plate code here
>> };
>>
>> something like
>>
>> DEFINE_MACHINE_EXTENDED(machine1, TYPE_WHATEVER_MACHINE, {INTERFACE1},
>> {INTERFACE2}, {})
>> DEFINE_MACHINE_EXTENDED(machine2, TYPE_OTHER_MACHINE, {INTERFACE1},
>> {INTERFACE3}, {})
>> DEFINE_MACHINE_EXTENDED(machine3, TYPE_THIRD_MACHINE, {INTERFACE1}, {})
>>
>
> Ok, I understand better.
>
> It was my point as well on v4, that introducing those symbols is less
> readable and less scalable, for a negligible benefit in terms of code
> size, which was the primary concern.
> We can always reconsider this later, especially when adding another
> architecture to single binary, it's not a problem and something set in
> stone.
>
> Would you be ok if we proceed with the current version, knowing those
> limitations, for now?
If Zoltan disagrees, we need Richard to agree to go back on v4.
Keep in mind that what we are trying to achieve is quite more complex
than code style or .rodata savings, besides we eventually want to have
dynamic machines & DSL.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-28 6:52 ` Philippe Mathieu-Daudé
@ 2025-04-28 10:31 ` BALATON Zoltan
2025-04-28 16:47 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-28 10:31 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Richard Henderson, Pierrick Bouvier, qemu-devel, Mark Cave-Ayland,
Anton Johansson
[-- Attachment #1: Type: text/plain, Size: 9327 bytes --]
On Mon, 28 Apr 2025, Philippe Mathieu-Daudé wrote:
> On 25/4/25 22:36, Pierrick Bouvier wrote:
>> On 4/25/25 13:29, BALATON Zoltan wrote:
>>> On Fri, 25 Apr 2025, Pierrick Bouvier wrote:
>>>> On 4/25/25 02:43, BALATON Zoltan wrote:
>>>>> On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
>>>>>> On 4/24/25 17:16, BALATON Zoltan wrote:
>>>>>>> On Fri, 25 Apr 2025, Philippe Mathieu-Daudé wrote:
>>>>>>>> A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro
>>>>>>>> will be available on qemu-system-arm and qemu-system-aarch64
>>>>>>>> binaries.
>>>>>>>>
>>>>>>>> One defined with DEFINE_MACHINE_AARCH64() will only be available
>>>>>>>> in the qemu-system-aarch64 binary.
>>>>>>>>
>>>>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>>>>>> ---
>>>>>>>> include/hw/arm/machines-qom.h | 13 +++++++++++++
>>>>>>>> target/arm/machine.c | 12 ++++++++++++
>>>>>>>> 2 files changed, 25 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/include/hw/arm/machines-qom.h
>>>>>>>> b/include/hw/arm/machines-qom.h
>>>>>>>> index a17225f5f92..6277ee986d9 100644
>>>>>>>> --- a/include/hw/arm/machines-qom.h
>>>>>>>> +++ b/include/hw/arm/machines-qom.h
>>>>>>>> @@ -9,10 +9,23 @@
>>>>>>>> #ifndef HW_ARM_MACHINES_QOM_H
>>>>>>>> #define HW_ARM_MACHINES_QOM_H
>>>>>>>>
>>>>>>>> +#include "hw/boards.h"
>>>>>>>> +
>>>>>>>> #define TYPE_TARGET_ARM_MACHINE \
>>>>>>>> "target-info-arm-machine"
>>>>>>>>
>>>>>>>> #define TYPE_TARGET_AARCH64_MACHINE \
>>>>>>>> "target-info-aarch64-machine"
>>>>>>>>
>>>>>>>> +extern InterfaceInfo arm_aarch64_machine_interfaces[];
>>>>>>>> +extern InterfaceInfo aarch64_machine_interfaces[];
>>>>>>>> +
>>>>>>>> +#define DEFINE_MACHINE_ARM_AARCH64(namestr, machine_initfn) \
>>>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>>>> +
>>>>>>>> arm_aarch64_machine_interfaces)
>>>>>>>> +
>>>>>>>> +#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
>>>>>>>> + DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, \
>>>>>>>> + aarch64_machine_interfaces)
>>>>>>>> +
>>>>>>>> #endif
>>>>>>>> diff --git a/target/arm/machine.c b/target/arm/machine.c
>>>>>>>> index 978249fb71b..193c7a9cff0 100644
>>>>>>>> --- a/target/arm/machine.c
>>>>>>>> +++ b/target/arm/machine.c
>>>>>>>> @@ -8,6 +8,7 @@
>>>>>>>> #include "cpu-features.h"
>>>>>>>> #include "migration/cpu.h"
>>>>>>>> #include "target/arm/gtimer.h"
>>>>>>>> +#include "hw/arm/machines-qom.h"
>>>>>>>>
>>>>>>>> static bool vfp_needed(void *opaque)
>>>>>>>> {
>>>>>>>> @@ -1111,3 +1112,14 @@ const VMStateDescription vmstate_arm_cpu = {
>>>>>>>> NULL
>>>>>>>> }
>>>>>>>> };
>>>>>>>> +
>>>>>>>> +InterfaceInfo arm_aarch64_machine_interfaces[] = {
>>>>>>>> + { TYPE_TARGET_ARM_MACHINE },
>>>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>>>> + { }
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +InterfaceInfo aarch64_machine_interfaces[] = {
>>>>>>>> + { TYPE_TARGET_AARCH64_MACHINE },
>>>>>>>> + { }
>>>>>>>> +};
>>>>>>>
>>>>>>> Why do you need these? If you define DEFINE_MACHINE_WITH_INTERFACES as
>>>>>>> OBJECT_DEFINE_TYPE_WITH_INTERFACES then you can write:
>>>>>>>
>>>>>>
>>>>>> This was requested in v4 by Richard to remove anonymous array
>>>>>> duplication
>>>>>> in
>>>>>> .data.
>>>>>>
>>>>>>> DEFINE_MACHINE_WITH_INTERFACES(name, initfn, { TYPE_TARGET_ARM_MACHINE
>>>>>>> },
>>>>>>> { TYPE_TARGET_AARCH64_MACHINE }, { })
>>>>>>>
>>>>>>> and no more macros needed. Ideally those places that are now blown up
>>>>>>> should use DEFINE_MACHINE too. Maybe they don't yet because the parent
>>>>>>> type is hardcoded so we should really have
>>>>>>>
>>>>>>
>>>>>> Not sure what you mean by "no more macros needed".
>>>>>
>>>>> No other specialised macros needed for each machine type other than
>>>>> DEFINE_MACHINE_WITH_INTERFACES or DEFINE_MACHINE_EXTENDED. So I
>>>>> suggested
>>>>> to keep DEFINE_MACHINE by making it more general so it can cover the new
>>>>> uses instead of bringing back the boiler plate and losing the clarity
>>>>> hinding these behind the macros.
>>>>>
>>>>
>>>> This is exactly what we have in this series.
>>>> Patch 7 introduces DEFINE_MACHINE_WITH_INTERFACES.
>>>> I guess Philippe chose a new name to avoid modifying all existing
>>>> DEFINE_MACHINE, and I think it's understandable, as we want those changes
>>>> to
>>>> impact hw/arm only first. That said, it would be very easy to
>>>> refactor/modify
>>>> later, so it's not a big deal.
>>>>
>>>> This patch introduces DEFINE_MACHINE_ARM_AARCH64 and
>>>> DEFINE_MACHINE_AARCH64.
>>>>
>>>> Is the problem with those specialized DEFINE_MACHINE_{ARM, AARCH64}
>>>> definition?
>>>> If yes, and if you prefer an explicit DEFINE_MACHINE_WITH_INTERFACES(...,
>>>> arm_aarch64_machine_interfaces), I'm sure Philippe would be open to make
>>>> such
>>>> a change to satisfy reviews.
>>>>
>>>> Let's just try to decide something, and move on.
>>>>
>>>>>> arm_aarch64_machine_interfaces or aarch64_machine_interfaces are arrays
>>>>>> (defined only once), which are passed as a parameter to
>>>>>> DEFINE_MACHINE_WITH_INTERFACES, or manually set with ".interfaces =".
>>>>>
>>>>> Look at how OBJECT_DEFINE_TYPE_WITH_INTERFACES is defined.
>>>>>
>>>>
>>>> This macro is not used for any machine definition so far, and
>>>> DEFINE_MACHINE
>>>> is the "standard" macro used, at least the one most commonly used in the
>>>> codebase. So it makes sense to simply expand the latter.
>>>
>>> I was referring to that as an example how a DEFINE_MACHINE_WITH_INTERFACES
>>> should work not suggesting to use OBJECT_DEFINE_TYPE_WITH_INTERFACES.
>>>
>>>>>>> DEFINE_MACHINE_EXTENDED(name, parent, initfn, interfaces...)
>>>>>>>
>>>>>>> and remove more bolier plate that way?
>>>>>>>
>>>>>>
>>>>>> Could you can share a concrete example of what you expect, with the new
>>>>>> macros to add, and how to use them for a given board?
>>>>>
>>>>> I tried to do that in this message you replied to.
>>>>>
>>>>
>>>> If you refer to "DEFINE_MACHINE_EXTENDED(name, parent, initfn,
>>>> interfaces...)", this is almost exactly what patch 7 is introducing with
>>>> DEFINE_MACHINE_WITH_INTERFACES(namestr, machine_initfn, ifaces).
>>>
>>> The difference is that OBJECT_DEFINE_TYPE_WITH_INTERFACES takes a list of
>>> interfaces and defines the array itself and you pass the array which is
>>> limiting as you then need to define a lot of arrays to pass to your macro
>>> instead of only passing the elements and let it define tha array.
>>>
>>> I just want to see instead of
>>>
>>> static const TypeInfo machine_types[] = {
>>> ...lots of boiler plate code here
>>> };
>>>
>>> something like
>>>
>>> DEFINE_MACHINE_EXTENDED(machine1, TYPE_WHATEVER_MACHINE, {INTERFACE1},
>>> {INTERFACE2}, {})
>>> DEFINE_MACHINE_EXTENDED(machine2, TYPE_OTHER_MACHINE, {INTERFACE1},
>>> {INTERFACE3}, {})
>>> DEFINE_MACHINE_EXTENDED(machine3, TYPE_THIRD_MACHINE, {INTERFACE1}, {})
>>>
>>
>> Ok, I understand better.
>>
>> It was my point as well on v4, that introducing those symbols is less
>> readable and less scalable, for a negligible benefit in terms of code size,
>> which was the primary concern.
>> We can always reconsider this later, especially when adding another
>> architecture to single binary, it's not a problem and something set in
>> stone.
>>
>> Would you be ok if we proceed with the current version, knowing those
>> limitations, for now?
>
> If Zoltan disagrees, we need Richard to agree to go back on v4.
>
> Keep in mind that what we are trying to achieve is quite more complex
> than code style or .rodata savings, besides we eventually want to have
> dynamic machines & DSL.
Since you are touching the lines using DEFINE_MACHINE it's a good
opportunity to change the macro to be more general to be able to keep
using it instead of replacing it with the boiler plate it's supposed to
hide. Adding one or two more parameters to the macro is not a big change
so I don't see why you don't want to do it. This could be addressed later
to revert to use the macro again but in practice it will not be addressed
because everybody will be busy doing other things and doing that now would
prevent some churn. I too, don't like doing unrelated clean up which is
not the main goal, but if it's not much more work then it's not
unreasonable to do it. I only oppose to that if it's a lot of work so I
would not ask such change but what I asked is not unrelated and quite
simple change.
That said, I can't stop you so if you still don't want to do it now then
you can move on. I don't care that much as long as you stay within hw/arm,
but will raise my concern again when you submit a similar patch that
touches parts I care more about. If others don't think it's a problem and
not bothered by the boiler plate code then it's not so important but
otherwise I think I have a valid point. I remember when I started to get
to know QEMU it was quite difficult to wade through all the QOM boiler
plate just to see what is related to the actual functionality. These
macros help to make code more readable and accessible for new people.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-28 10:31 ` BALATON Zoltan
@ 2025-04-28 16:47 ` Pierrick Bouvier
2025-04-28 18:44 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-28 16:47 UTC (permalink / raw)
To: BALATON Zoltan, Philippe Mathieu-Daudé
Cc: Richard Henderson, qemu-devel, Mark Cave-Ayland, Anton Johansson
On 4/28/25 3:31 AM, BALATON Zoltan wrote:
> Since you are touching the lines using DEFINE_MACHINE it's a good
> opportunity to change the macro to be more general to be able to keep
> using it instead of replacing it with the boiler plate it's supposed to
> hide. Adding one or two more parameters to the macro is not a big change
> so I don't see why you don't want to do it. This could be addressed later
> to revert to use the macro again but in practice it will not be addressed
> because everybody will be busy doing other things and doing that now would
> prevent some churn. I too, don't like doing unrelated clean up which is
> not the main goal, but if it's not much more work then it's not
> unreasonable to do it. I only oppose to that if it's a lot of work so I
> would not ask such change but what I asked is not unrelated and quite
> simple change.
>
> That said, I can't stop you so if you still don't want to do it now then
> you can move on. I don't care that much as long as you stay within hw/arm,
> but will raise my concern again when you submit a similar patch that
> touches parts I care more about. If others don't think it's a problem and
> not bothered by the boiler plate code then it's not so important but
> otherwise I think I have a valid point. I remember when I started to get
> to know QEMU it was quite difficult to wade through all the QOM boiler
> plate just to see what is related to the actual functionality. These
> macros help to make code more readable and accessible for new people.
>
Having been through that recently, I agree with you that it can be hard
to follow at first. Luckily, we have perfect compiler based completion
for all editors those days (I sincerely hope everyone spent 2 hours
configuring this on their own favorite one), and it's easy to see where
things are defined and used, even when code is cryptic.
That said, pushing to someone adding a new field the responsibility of
cleaning up the whole thing is not a fair request. You can't expect your
friends to clean your shared house because they brought a cake for dinner.
> Regards,
> BALATON Zoltan
Regards,
Pierrick
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-28 16:47 ` Pierrick Bouvier
@ 2025-04-28 18:44 ` BALATON Zoltan
2025-04-28 19:09 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-28 18:44 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>> Since you are touching the lines using DEFINE_MACHINE it's a good
>> opportunity to change the macro to be more general to be able to keep
>> using it instead of replacing it with the boiler plate it's supposed to
>> hide. Adding one or two more parameters to the macro is not a big change
>> so I don't see why you don't want to do it. This could be addressed later
>> to revert to use the macro again but in practice it will not be addressed
>> because everybody will be busy doing other things and doing that now would
>> prevent some churn. I too, don't like doing unrelated clean up which is
>> not the main goal, but if it's not much more work then it's not
>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>> would not ask such change but what I asked is not unrelated and quite
>> simple change.
>>
>> That said, I can't stop you so if you still don't want to do it now then
>> you can move on. I don't care that much as long as you stay within hw/arm,
>> but will raise my concern again when you submit a similar patch that
>> touches parts I care more about. If others don't think it's a problem and
>> not bothered by the boiler plate code then it's not so important but
>> otherwise I think I have a valid point. I remember when I started to get
>> to know QEMU it was quite difficult to wade through all the QOM boiler
>> plate just to see what is related to the actual functionality. These
>> macros help to make code more readable and accessible for new people.
>
> Having been through that recently, I agree with you that it can be hard to
> follow at first. Luckily, we have perfect compiler based completion for all
> editors those days (I sincerely hope everyone spent 2 hours configuring this
> on their own favorite one), and it's easy to see where things are defined and
> used, even when code is cryptic.
It's not about typing but reading it. The verbose struct definitions are
hard to follow and makes board code look more complex than it should be.
> That said, pushing to someone adding a new field the responsibility of
> cleaning up the whole thing is not a fair request. You can't expect your
> friends to clean your shared house because they brought a cake for dinner.
I tend to get such requests to clean up unrelated things whenever I try to
change anything in PPC Mac emulation which I also complain about and think
is not reasonable to ask. But I did not ask for unrelated cleanup here and
changing the patch so you don't do this:
-DEFINE_MACHINE("none", machine_none_machine_init)
+static const TypeInfo null_machine_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("none"),
+ .parent = TYPE_MACHINE,
+ .class_init = null_machine_class_init,
+ },
+};
+
+DEFINE_TYPES(null_machine_types)
but instead add the .interfaces field to a variant of DEFINE_MACHINE once
and keep the one line definition is not something unreasonable to ask. I
think you can ask your friends to not make a mess in the shared house
while having a party or at least clean up after that. Adding one more
parameter to the macro is also simple to do so I don't get why you're so
opposed to this.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-28 18:44 ` BALATON Zoltan
@ 2025-04-28 19:09 ` Pierrick Bouvier
2025-04-29 1:10 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-28 19:09 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On 4/28/25 11:44 AM, BALATON Zoltan wrote:
> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>>> Since you are touching the lines using DEFINE_MACHINE it's a good
>>> opportunity to change the macro to be more general to be able to keep
>>> using it instead of replacing it with the boiler plate it's supposed to
>>> hide. Adding one or two more parameters to the macro is not a big change
>>> so I don't see why you don't want to do it. This could be addressed later
>>> to revert to use the macro again but in practice it will not be addressed
>>> because everybody will be busy doing other things and doing that now would
>>> prevent some churn. I too, don't like doing unrelated clean up which is
>>> not the main goal, but if it's not much more work then it's not
>>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>>> would not ask such change but what I asked is not unrelated and quite
>>> simple change.
>>>
>>> That said, I can't stop you so if you still don't want to do it now then
>>> you can move on. I don't care that much as long as you stay within hw/arm,
>>> but will raise my concern again when you submit a similar patch that
>>> touches parts I care more about. If others don't think it's a problem and
>>> not bothered by the boiler plate code then it's not so important but
>>> otherwise I think I have a valid point. I remember when I started to get
>>> to know QEMU it was quite difficult to wade through all the QOM boiler
>>> plate just to see what is related to the actual functionality. These
>>> macros help to make code more readable and accessible for new people.
>>
>> Having been through that recently, I agree with you that it can be hard to
>> follow at first. Luckily, we have perfect compiler based completion for all
>> editors those days (I sincerely hope everyone spent 2 hours configuring this
>> on their own favorite one), and it's easy to see where things are defined and
>> used, even when code is cryptic.
>
> It's not about typing but reading it. The verbose struct definitions are
> hard to follow and makes board code look more complex than it should be.
>
>> That said, pushing to someone adding a new field the responsibility of
>> cleaning up the whole thing is not a fair request. You can't expect your
>> friends to clean your shared house because they brought a cake for dinner.
>
> I tend to get such requests to clean up unrelated things whenever I try to
> change anything in PPC Mac emulation which I also complain about and think
> is not reasonable to ask. But I did not ask for unrelated cleanup here and
> changing the patch so you don't do this:
>
> -DEFINE_MACHINE("none", machine_none_machine_init)
> +static const TypeInfo null_machine_types[] = {
> + {
> + .name = MACHINE_TYPE_NAME("none"),
> + .parent = TYPE_MACHINE,
> + .class_init = null_machine_class_init,
> + },
> +};
> +
> +DEFINE_TYPES(null_machine_types)
>
> but instead add the .interfaces field to a variant of DEFINE_MACHINE once
> and keep the one line definition is not something unreasonable to ask. I
> think you can ask your friends to not make a mess in the shared house
> while having a party or at least clean up after that. Adding one more
> parameter to the macro is also simple to do so I don't get why you're so
> opposed to this.
>
Maybe there is a misunderstanding on my side, but it seems that what you
asked is exactly patch 7, which introduce DEFINE_MACHINE_WITH_INTERFACES.
That said, patch 4 ("hw/core/null-machine: Define machine as generic QOM
type") could use it to define the null machine. Philippe, could you
change patch 4 to use DEFINE_MACHINE_WITH_INTERFACES instead?
Thanks,
Pierrick
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-28 19:09 ` Pierrick Bouvier
@ 2025-04-29 1:10 ` BALATON Zoltan
2025-04-29 1:21 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-04-29 1:10 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
> On 4/28/25 11:44 AM, BALATON Zoltan wrote:
>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>>>> Since you are touching the lines using DEFINE_MACHINE it's a good
>>>> opportunity to change the macro to be more general to be able to keep
>>>> using it instead of replacing it with the boiler plate it's supposed to
>>>> hide. Adding one or two more parameters to the macro is not a big change
>>>> so I don't see why you don't want to do it. This could be addressed later
>>>> to revert to use the macro again but in practice it will not be addressed
>>>> because everybody will be busy doing other things and doing that now
>>>> would
>>>> prevent some churn. I too, don't like doing unrelated clean up which is
>>>> not the main goal, but if it's not much more work then it's not
>>>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>>>> would not ask such change but what I asked is not unrelated and quite
>>>> simple change.
>>>>
>>>> That said, I can't stop you so if you still don't want to do it now then
>>>> you can move on. I don't care that much as long as you stay within
>>>> hw/arm,
>>>> but will raise my concern again when you submit a similar patch that
>>>> touches parts I care more about. If others don't think it's a problem and
>>>> not bothered by the boiler plate code then it's not so important but
>>>> otherwise I think I have a valid point. I remember when I started to get
>>>> to know QEMU it was quite difficult to wade through all the QOM boiler
>>>> plate just to see what is related to the actual functionality. These
>>>> macros help to make code more readable and accessible for new people.
>>>
>>> Having been through that recently, I agree with you that it can be hard to
>>> follow at first. Luckily, we have perfect compiler based completion for
>>> all
>>> editors those days (I sincerely hope everyone spent 2 hours configuring
>>> this
>>> on their own favorite one), and it's easy to see where things are defined
>>> and
>>> used, even when code is cryptic.
>>
>> It's not about typing but reading it. The verbose struct definitions are
>> hard to follow and makes board code look more complex than it should be.
>>
>>> That said, pushing to someone adding a new field the responsibility of
>>> cleaning up the whole thing is not a fair request. You can't expect your
>>> friends to clean your shared house because they brought a cake for dinner.
>>
>> I tend to get such requests to clean up unrelated things whenever I try to
>> change anything in PPC Mac emulation which I also complain about and think
>> is not reasonable to ask. But I did not ask for unrelated cleanup here and
>> changing the patch so you don't do this:
>>
>> -DEFINE_MACHINE("none", machine_none_machine_init)
>> +static const TypeInfo null_machine_types[] = {
>> + {
>> + .name = MACHINE_TYPE_NAME("none"),
>> + .parent = TYPE_MACHINE,
>> + .class_init = null_machine_class_init,
>> + },
>> +};
>> +
>> +DEFINE_TYPES(null_machine_types)
>>
>> but instead add the .interfaces field to a variant of DEFINE_MACHINE once
>> and keep the one line definition is not something unreasonable to ask. I
>> think you can ask your friends to not make a mess in the shared house
>> while having a party or at least clean up after that. Adding one more
>> parameter to the macro is also simple to do so I don't get why you're so
>> opposed to this.
>>
>
> Maybe there is a misunderstanding on my side, but it seems that what you
> asked is exactly patch 7, which introduce DEFINE_MACHINE_WITH_INTERFACES.
Almost but not quite. I don't know why I can't get this through to you. If
you compare patch 7 to how DO_OBJECT_DEFINE_TYPE_EXTENDED is defined do
you notice the difference in how .interfaces is set? With the same way as
in DO_OBJECT_DEFINE_TYPE_EXTENDED you don't need separate InterfaceInfo
arm_aarch64_machine_interfaces[] definitions or different macros in the
next patch just list the needed interfaces in the machine definitions.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-29 1:10 ` BALATON Zoltan
@ 2025-04-29 1:21 ` Pierrick Bouvier
2025-05-01 23:35 ` BALATON Zoltan
0 siblings, 1 reply; 47+ messages in thread
From: Pierrick Bouvier @ 2025-04-29 1:21 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On 4/28/25 6:10 PM, BALATON Zoltan wrote:
> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>> On 4/28/25 11:44 AM, BALATON Zoltan wrote:
>>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>>> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>>>>> Since you are touching the lines using DEFINE_MACHINE it's a good
>>>>> opportunity to change the macro to be more general to be able to keep
>>>>> using it instead of replacing it with the boiler plate it's supposed to
>>>>> hide. Adding one or two more parameters to the macro is not a big change
>>>>> so I don't see why you don't want to do it. This could be addressed later
>>>>> to revert to use the macro again but in practice it will not be addressed
>>>>> because everybody will be busy doing other things and doing that now
>>>>> would
>>>>> prevent some churn. I too, don't like doing unrelated clean up which is
>>>>> not the main goal, but if it's not much more work then it's not
>>>>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>>>>> would not ask such change but what I asked is not unrelated and quite
>>>>> simple change.
>>>>>
>>>>> That said, I can't stop you so if you still don't want to do it now then
>>>>> you can move on. I don't care that much as long as you stay within
>>>>> hw/arm,
>>>>> but will raise my concern again when you submit a similar patch that
>>>>> touches parts I care more about. If others don't think it's a problem and
>>>>> not bothered by the boiler plate code then it's not so important but
>>>>> otherwise I think I have a valid point. I remember when I started to get
>>>>> to know QEMU it was quite difficult to wade through all the QOM boiler
>>>>> plate just to see what is related to the actual functionality. These
>>>>> macros help to make code more readable and accessible for new people.
>>>>
>>>> Having been through that recently, I agree with you that it can be hard to
>>>> follow at first. Luckily, we have perfect compiler based completion for
>>>> all
>>>> editors those days (I sincerely hope everyone spent 2 hours configuring
>>>> this
>>>> on their own favorite one), and it's easy to see where things are defined
>>>> and
>>>> used, even when code is cryptic.
>>>
>>> It's not about typing but reading it. The verbose struct definitions are
>>> hard to follow and makes board code look more complex than it should be.
>>>
>>>> That said, pushing to someone adding a new field the responsibility of
>>>> cleaning up the whole thing is not a fair request. You can't expect your
>>>> friends to clean your shared house because they brought a cake for dinner.
>>>
>>> I tend to get such requests to clean up unrelated things whenever I try to
>>> change anything in PPC Mac emulation which I also complain about and think
>>> is not reasonable to ask. But I did not ask for unrelated cleanup here and
>>> changing the patch so you don't do this:
>>>
>>> -DEFINE_MACHINE("none", machine_none_machine_init)
>>> +static const TypeInfo null_machine_types[] = {
>>> + {
>>> + .name = MACHINE_TYPE_NAME("none"),
>>> + .parent = TYPE_MACHINE,
>>> + .class_init = null_machine_class_init,
>>> + },
>>> +};
>>> +
>>> +DEFINE_TYPES(null_machine_types)
>>>
>>> but instead add the .interfaces field to a variant of DEFINE_MACHINE once
>>> and keep the one line definition is not something unreasonable to ask. I
>>> think you can ask your friends to not make a mess in the shared house
>>> while having a party or at least clean up after that. Adding one more
>>> parameter to the macro is also simple to do so I don't get why you're so
>>> opposed to this.
>>>
>>
>> Maybe there is a misunderstanding on my side, but it seems that what you
>> asked is exactly patch 7, which introduce DEFINE_MACHINE_WITH_INTERFACES.
>
> Almost but not quite. I don't know why I can't get this through to you. If
> you compare patch 7 to how DO_OBJECT_DEFINE_TYPE_EXTENDED is defined do
> you notice the difference in how .interfaces is set? With the same way as
> in DO_OBJECT_DEFINE_TYPE_EXTENDED you don't need separate InterfaceInfo
> arm_aarch64_machine_interfaces[] definitions or different macros in the
> next patch just list the needed interfaces in the machine definitions.
>
I'm sorry, I don't understand what you want exactly, despite asking
several times.
I think it would be more clear if you could apply this series on your
side, write a small patch showing *exactly* what you expect, and
applying this to one of the board concerned. Then, we can do the change
you request.
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-04-29 1:21 ` Pierrick Bouvier
@ 2025-05-01 23:35 ` BALATON Zoltan
2025-05-03 19:38 ` Pierrick Bouvier
0 siblings, 1 reply; 47+ messages in thread
From: BALATON Zoltan @ 2025-05-01 23:35 UTC (permalink / raw)
To: Pierrick Bouvier
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
> On 4/28/25 6:10 PM, BALATON Zoltan wrote:
>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>> On 4/28/25 11:44 AM, BALATON Zoltan wrote:
>>>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>>>> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>>>>>> Since you are touching the lines using DEFINE_MACHINE it's a good
>>>>>> opportunity to change the macro to be more general to be able to keep
>>>>>> using it instead of replacing it with the boiler plate it's supposed to
>>>>>> hide. Adding one or two more parameters to the macro is not a big
>>>>>> change
>>>>>> so I don't see why you don't want to do it. This could be addressed
>>>>>> later
>>>>>> to revert to use the macro again but in practice it will not be
>>>>>> addressed
>>>>>> because everybody will be busy doing other things and doing that now
>>>>>> would
>>>>>> prevent some churn. I too, don't like doing unrelated clean up which is
>>>>>> not the main goal, but if it's not much more work then it's not
>>>>>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>>>>>> would not ask such change but what I asked is not unrelated and quite
>>>>>> simple change.
>>>>>>
>>>>>> That said, I can't stop you so if you still don't want to do it now
>>>>>> then
>>>>>> you can move on. I don't care that much as long as you stay within
>>>>>> hw/arm,
>>>>>> but will raise my concern again when you submit a similar patch that
>>>>>> touches parts I care more about. If others don't think it's a problem
>>>>>> and
>>>>>> not bothered by the boiler plate code then it's not so important but
>>>>>> otherwise I think I have a valid point. I remember when I started to
>>>>>> get
>>>>>> to know QEMU it was quite difficult to wade through all the QOM boiler
>>>>>> plate just to see what is related to the actual functionality. These
>>>>>> macros help to make code more readable and accessible for new people.
>>>>>
>>>>> Having been through that recently, I agree with you that it can be hard
>>>>> to
>>>>> follow at first. Luckily, we have perfect compiler based completion for
>>>>> all
>>>>> editors those days (I sincerely hope everyone spent 2 hours configuring
>>>>> this
>>>>> on their own favorite one), and it's easy to see where things are
>>>>> defined
>>>>> and
>>>>> used, even when code is cryptic.
>>>>
>>>> It's not about typing but reading it. The verbose struct definitions are
>>>> hard to follow and makes board code look more complex than it should be.
>>>>
>>>>> That said, pushing to someone adding a new field the responsibility of
>>>>> cleaning up the whole thing is not a fair request. You can't expect your
>>>>> friends to clean your shared house because they brought a cake for
>>>>> dinner.
>>>>
>>>> I tend to get such requests to clean up unrelated things whenever I try
>>>> to
>>>> change anything in PPC Mac emulation which I also complain about and
>>>> think
>>>> is not reasonable to ask. But I did not ask for unrelated cleanup here
>>>> and
>>>> changing the patch so you don't do this:
>>>>
>>>> -DEFINE_MACHINE("none", machine_none_machine_init)
>>>> +static const TypeInfo null_machine_types[] = {
>>>> + {
>>>> + .name = MACHINE_TYPE_NAME("none"),
>>>> + .parent = TYPE_MACHINE,
>>>> + .class_init = null_machine_class_init,
>>>> + },
>>>> +};
>>>> +
>>>> +DEFINE_TYPES(null_machine_types)
>>>>
>>>> but instead add the .interfaces field to a variant of DEFINE_MACHINE once
>>>> and keep the one line definition is not something unreasonable to ask. I
>>>> think you can ask your friends to not make a mess in the shared house
>>>> while having a party or at least clean up after that. Adding one more
>>>> parameter to the macro is also simple to do so I don't get why you're so
>>>> opposed to this.
>>>>
>>>
>>> Maybe there is a misunderstanding on my side, but it seems that what you
>>> asked is exactly patch 7, which introduce DEFINE_MACHINE_WITH_INTERFACES.
>>
>> Almost but not quite. I don't know why I can't get this through to you. If
>> you compare patch 7 to how DO_OBJECT_DEFINE_TYPE_EXTENDED is defined do
>> you notice the difference in how .interfaces is set? With the same way as
>> in DO_OBJECT_DEFINE_TYPE_EXTENDED you don't need separate InterfaceInfo
>> arm_aarch64_machine_interfaces[] definitions or different macros in the
>> next patch just list the needed interfaces in the machine definitions.
>>
>
> I'm sorry, I don't understand what you want exactly, despite asking several
> times.
> I think it would be more clear if you could apply this series on your side,
> write a small patch showing *exactly* what you expect, and applying this to
> one of the board concerned. Then, we can do the change you request.
You can pick the patch from this series I've just posted:
https://patchew.org/QEMU/cover.1746139668.git.balaton@eik.bme.hu/ad355178b2a3fe285854ed2e25b288baf0fd6e05.1746139668.git.balaton@eik.bme.hu/
it is used in patch 12 of that series for an example.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
2025-05-01 23:35 ` BALATON Zoltan
@ 2025-05-03 19:38 ` Pierrick Bouvier
0 siblings, 0 replies; 47+ messages in thread
From: Pierrick Bouvier @ 2025-05-03 19:38 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel,
Mark Cave-Ayland, Anton Johansson
On 5/1/25 4:35 PM, BALATON Zoltan wrote:
> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>> On 4/28/25 6:10 PM, BALATON Zoltan wrote:
>>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>>> On 4/28/25 11:44 AM, BALATON Zoltan wrote:
>>>>> On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
>>>>>> On 4/28/25 3:31 AM, BALATON Zoltan wrote:
>>>>>>> Since you are touching the lines using DEFINE_MACHINE it's a good
>>>>>>> opportunity to change the macro to be more general to be able to keep
>>>>>>> using it instead of replacing it with the boiler plate it's supposed to
>>>>>>> hide. Adding one or two more parameters to the macro is not a big
>>>>>>> change
>>>>>>> so I don't see why you don't want to do it. This could be addressed
>>>>>>> later
>>>>>>> to revert to use the macro again but in practice it will not be
>>>>>>> addressed
>>>>>>> because everybody will be busy doing other things and doing that now
>>>>>>> would
>>>>>>> prevent some churn. I too, don't like doing unrelated clean up which is
>>>>>>> not the main goal, but if it's not much more work then it's not
>>>>>>> unreasonable to do it. I only oppose to that if it's a lot of work so I
>>>>>>> would not ask such change but what I asked is not unrelated and quite
>>>>>>> simple change.
>>>>>>>
>>>>>>> That said, I can't stop you so if you still don't want to do it now
>>>>>>> then
>>>>>>> you can move on. I don't care that much as long as you stay within
>>>>>>> hw/arm,
>>>>>>> but will raise my concern again when you submit a similar patch that
>>>>>>> touches parts I care more about. If others don't think it's a problem
>>>>>>> and
>>>>>>> not bothered by the boiler plate code then it's not so important but
>>>>>>> otherwise I think I have a valid point. I remember when I started to
>>>>>>> get
>>>>>>> to know QEMU it was quite difficult to wade through all the QOM boiler
>>>>>>> plate just to see what is related to the actual functionality. These
>>>>>>> macros help to make code more readable and accessible for new people.
>>>>>>
>>>>>> Having been through that recently, I agree with you that it can be hard
>>>>>> to
>>>>>> follow at first. Luckily, we have perfect compiler based completion for
>>>>>> all
>>>>>> editors those days (I sincerely hope everyone spent 2 hours configuring
>>>>>> this
>>>>>> on their own favorite one), and it's easy to see where things are
>>>>>> defined
>>>>>> and
>>>>>> used, even when code is cryptic.
>>>>>
>>>>> It's not about typing but reading it. The verbose struct definitions are
>>>>> hard to follow and makes board code look more complex than it should be.
>>>>>
>>>>>> That said, pushing to someone adding a new field the responsibility of
>>>>>> cleaning up the whole thing is not a fair request. You can't expect your
>>>>>> friends to clean your shared house because they brought a cake for
>>>>>> dinner.
>>>>>
>>>>> I tend to get such requests to clean up unrelated things whenever I try
>>>>> to
>>>>> change anything in PPC Mac emulation which I also complain about and
>>>>> think
>>>>> is not reasonable to ask. But I did not ask for unrelated cleanup here
>>>>> and
>>>>> changing the patch so you don't do this:
>>>>>
>>>>> -DEFINE_MACHINE("none", machine_none_machine_init)
>>>>> +static const TypeInfo null_machine_types[] = {
>>>>> + {
>>>>> + .name = MACHINE_TYPE_NAME("none"),
>>>>> + .parent = TYPE_MACHINE,
>>>>> + .class_init = null_machine_class_init,
>>>>> + },
>>>>> +};
>>>>> +
>>>>> +DEFINE_TYPES(null_machine_types)
>>>>>
>>>>> but instead add the .interfaces field to a variant of DEFINE_MACHINE once
>>>>> and keep the one line definition is not something unreasonable to ask. I
>>>>> think you can ask your friends to not make a mess in the shared house
>>>>> while having a party or at least clean up after that. Adding one more
>>>>> parameter to the macro is also simple to do so I don't get why you're so
>>>>> opposed to this.
>>>>>
>>>>
>>>> Maybe there is a misunderstanding on my side, but it seems that what you
>>>> asked is exactly patch 7, which introduce DEFINE_MACHINE_WITH_INTERFACES.
>>>
>>> Almost but not quite. I don't know why I can't get this through to you. If
>>> you compare patch 7 to how DO_OBJECT_DEFINE_TYPE_EXTENDED is defined do
>>> you notice the difference in how .interfaces is set? With the same way as
>>> in DO_OBJECT_DEFINE_TYPE_EXTENDED you don't need separate InterfaceInfo
>>> arm_aarch64_machine_interfaces[] definitions or different macros in the
>>> next patch just list the needed interfaces in the machine definitions.
>>>
>>
>> I'm sorry, I don't understand what you want exactly, despite asking several
>> times.
>> I think it would be more clear if you could apply this series on your side,
>> write a small patch showing *exactly* what you expect, and applying this to
>> one of the board concerned. Then, we can do the change you request.
>
> You can pick the patch from this series I've just posted:
> https://patchew.org/QEMU/cover.1746139668.git.balaton@eik.bme.hu/ad355178b2a3fe285854ed2e25b288baf0fd6e05.1746139668.git.balaton@eik.bme.hu/
> it is used in patch 12 of that series for an example.
>
Sounds good, thanks.
@Philippe, could you cherry-pick this patch as part of next iteration?
> Regards,
> BALATON Zoltan
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2025-05-03 19:38 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
2025-04-24 22:30 ` Pierrick Bouvier
2025-04-24 22:47 ` Philippe Mathieu-Daudé
2025-04-24 22:49 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
2025-04-24 22:44 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
2025-04-24 22:35 ` Pierrick Bouvier
2025-04-24 22:45 ` Philippe Mathieu-Daudé
2025-04-25 0:16 ` BALATON Zoltan
2025-04-25 6:05 ` Pierrick Bouvier
2025-04-25 9:43 ` BALATON Zoltan
2025-04-25 20:05 ` Pierrick Bouvier
2025-04-25 20:29 ` BALATON Zoltan
2025-04-25 20:36 ` Pierrick Bouvier
2025-04-28 6:52 ` Philippe Mathieu-Daudé
2025-04-28 10:31 ` BALATON Zoltan
2025-04-28 16:47 ` Pierrick Bouvier
2025-04-28 18:44 ` BALATON Zoltan
2025-04-28 19:09 ` Pierrick Bouvier
2025-04-29 1:10 ` BALATON Zoltan
2025-04-29 1:21 ` Pierrick Bouvier
2025-05-01 23:35 ` BALATON Zoltan
2025-05-03 19:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 13/21] hw/arm/raspi: " Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
2025-04-24 22:43 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
2025-04-24 22:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
2025-04-24 22:39 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
2025-04-28 3:19 ` Zhang Chen
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