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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cd935931ebsm631684f8f.55.2025.08.27.09.28.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Aug 2025 09:28:54 -0700 (PDT) Message-ID: Date: Wed, 27 Aug 2025 18:28:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 13/21] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Content-Language: en-US To: Zhenzhong Duan , qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun References: <20250822064101.123526-1-zhenzhong.duan@intel.com> <20250822064101.123526-14-zhenzhong.duan@intel.com> From: Eric Auger In-Reply-To: <20250822064101.123526-14-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Zhenzhong, On 8/22/25 8:40 AM, Zhenzhong Duan wrote: > FORCE_RESET is different from GLOBAL_INV which updates pasid cache if > underlying pasid entry is still valid, it drops all the pasid caches. > > FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, > only used internally in system level reset. > > Signed-off-by: Yi Liu > Signed-off-by: Yi Sun > Signed-off-by: Zhenzhong Duan > --- > hw/i386/intel_iommu_internal.h | 9 +++++++++ > hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ > hw/i386/trace-events | 1 + > 3 files changed, 35 insertions(+) > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index fb2a919e87..c510b09d1a 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -569,6 +569,15 @@ typedef enum VTDPCInvType { > VTD_PASID_CACHE_DOMSI = VTD_INV_DESC_PASIDC_G_DSI, > VTD_PASID_CACHE_PASIDSI = VTD_INV_DESC_PASIDC_G_PASID_SI, > VTD_PASID_CACHE_GLOBAL_INV = VTD_INV_DESC_PASIDC_G_GLOBAL, > + > + /* > + * Internally used PASID cache invalidation type starts here, > + * 0x10 is large enough as invalidation type in pc_inv_desc > + * is 2bits in size. > + */ > + > + /* Reset all PASID cache entries, used in system level reset */ > + VTD_PASID_CACHE_FORCE_RESET = 0x10, I am not very keen on adding such an artifical enum value that does not exist in the spec. Why not simply introduce another function (instead of vtd_flush_pasid_locked) that does the cleanup. To me it would be cleaner. Thanks Eric > } VTDPCInvType; > > typedef struct VTDPASIDCacheInfo { > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 7d2c9feae7..af384ce7f0 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -87,6 +87,8 @@ struct vtd_iotlb_key { > static void vtd_address_space_refresh_all(IntelIOMMUState *s); > static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); > > +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); > + > static void vtd_panic_require_caching_mode(void) > { > error_report("We need to set caching-mode=on for intel-iommu to enable " > @@ -391,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) > vtd_iommu_lock(s); > vtd_reset_iotlb_locked(s); > vtd_reset_context_cache_locked(s); > + vtd_pasid_cache_reset_locked(s); > vtd_iommu_unlock(s); > } > > @@ -3183,6 +3186,8 @@ static gboolean vtd_flush_pasid_locked(gpointer key, gpointer value, > /* fall through */ > case VTD_PASID_CACHE_GLOBAL_INV: > break; > + case VTD_PASID_CACHE_FORCE_RESET: > + goto remove; > default: > error_setg(&error_fatal, "invalid pc_info->type for flush"); > } > @@ -3225,6 +3230,23 @@ remove: > return true; > } > > +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) > +{ > + VTDPASIDCacheInfo pc_info; > + > + trace_vtd_pasid_cache_reset(); > + > + pc_info.type = VTD_PASID_CACHE_FORCE_RESET; > + > + /* > + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remove > + * which will free all vtd_as instances except those created for PCI > + * sub-system. > + */ > + g_hash_table_foreach_remove(s->vtd_address_spaces, > + vtd_flush_pasid_locked, &pc_info); > +} > + > /* > * This function walks over PASID range within [start, end) in a single > * PASID table for entries matching @info type/did, then retrieve/create > @@ -3363,6 +3385,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, > case VTD_PASID_CACHE_GLOBAL_INV: > /* loop all assigned devices */ > break; > + case VTD_PASID_CACHE_FORCE_RESET: > + /* For force reset, no need to go further replay */ > + return; > default: > error_setg(&error_fatal, "invalid pc_info->type for replay"); > } > diff --git a/hw/i386/trace-events b/hw/i386/trace-events > index ae5bbfcdc0..c8a936eb46 100644 > --- a/hw/i386/trace-events > +++ b/hw/i386/trace-events > @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" > vtd_inv_qi_tail(uint16_t head) "write tail %d" > vtd_inv_qi_fetch(void) "" > vtd_context_cache_reset(void) "" > +vtd_pasid_cache_reset(void) "" > vtd_pasid_cache_gsi(void) "" > vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation domain 0x%"PRIx16 > vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32