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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39eaf43cd17sm11672174f8f.78.2025.04.14.10.38.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Apr 2025 10:38:04 -0700 (PDT) Message-ID: Date: Mon, 14 Apr 2025 19:38:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] target/riscv: fix endless translation loop on big endian systems To: Ziqiao Kong Cc: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Paolo Bonzini References: <20250414034626.3491489-1-ziqiaokong@gmail.com> <20250414034626.3491489-2-ziqiaokong@gmail.com> <3c9e1adc-eb4e-49f4-be32-b273a5a161b8@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 14/4/25 18:59, Ziqiao Kong wrote: > Hello Philippe, > > Any further concern regarding this series? I certainly would like to investigate > and help =). Short term I can't keep looking because I'm busy with other stuffs and tagged this patch for another review, because there is some endianness code smell in get_physical_address(). I understand your change fixes your issue, but I'm skeptical about it, in part because there are no such use in the whole code base. My change suggestion is just a starting point, more is needed. > > Bests, > Ziqiao > > On Mon, Apr 14, 2025 at 7:17 PM Ziqiao Kong wrote: >> >> On Mon, Apr 14, 2025 at 6:41 PM Philippe Mathieu-Daudé >> wrote: >>> >>> Hi, >>> >>> On 14/4/25 05:46, Ziqiao Kong wrote: >>>> On big endian systems, pte and updated_pte hold big endian host data >>>> while pte_pa points to little endian target data. This means the branch >>>> at cpu_helper.c:1669 will be always satisfied and restart translation, >>>> causing an endless translation loop. >>>> >>> >>> Cc: qemu-stable@nongnu.org >>> Fixes: 0c3e702aca7 ("RISC-V CPU Helpers") >>> >>>> Signed-off-by: Ziqiao Kong >>>> --- >>>> target/riscv/cpu_helper.c | 4 ++-- >>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>>> index 6c4391d96b..bc146771c8 100644 >>>> --- a/target/riscv/cpu_helper.c >>>> +++ b/target/riscv/cpu_helper.c >>>> @@ -1662,9 +1662,9 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, >>>> target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); >>>> target_ulong old_pte; >>>> if (riscv_cpu_sxl(env) == MXL_RV32) { >>>> - old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte); >>>> + old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pte), cpu_to_le32(updated_pte)); >>>> } else { >>>> - old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); >>>> + old_pte = qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_to_le64(updated_pte)); >>>> } >>>> if (old_pte != pte) { >>>> goto restart; >>> >>> If PTEs are always stored in LE order, maybe what we want is earlier: >>> >>> -- >8 -- >>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>> index 619c76cc001..b6ac2800240 100644 >>> --- a/target/riscv/cpu_helper.c >>> +++ b/target/riscv/cpu_helper.c >>> @@ -1464,5 +1464,5 @@ static int get_physical_address(CPURISCVState >>> *env, hwaddr *physical, >>> if (riscv_cpu_mxl(env) == MXL_RV32) { >>> - pte = address_space_ldl(cs->as, pte_addr, attrs, &res); >>> + pte = address_space_ldl_le(cs->as, pte_addr, attrs, &res); >>> } else { >>> - pte = address_space_ldq(cs->as, pte_addr, attrs, &res); >>> + pte = address_space_ldq_le(cs->as, pte_addr, attrs, &res); >> >> Unfortunately, this doesn't work in two ways: >> >> 1. Note pte is used in the following code and that means pte must hold >> a correct value from the >> view of host endian (in my case, big endian not little endian). >> 2. address_space_ldq_le will dispatch to ldq_le_p, while >> address_space_leq will dispatch to ldq_p. >> However, on little endian targets, ldq_p is an alias of ldq_le_p so >> making no effects. >> >> Per my testing, this patch doesn't have any effect indeed. To have a >> brief view what is happening, >> see the logs just before atomic_cmpxchg: >> >> pte_pa 0xf14000000000000 == pte 0x140f ? updated_pte 0x144f >> >>> } >>> ---