From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Marcin Nowakowski <marcin.nowakowski@fungible.com>,
qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Subject: Re: [PATCH v2 3/4] target/mips: implement CP0.Config7.WII bit support
Date: Thu, 16 Feb 2023 09:08:15 +0100 [thread overview]
Message-ID: <c57ec7ad-a3b9-c698-e320-3798ffa4fdaa@linaro.org> (raw)
In-Reply-To: <20230216051717.3911212-4-marcin.nowakowski@fungible.com>
On 16/2/23 06:17, Marcin Nowakowski wrote:
> Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a
> disabled interrupt should wake up a sleeping CPU.
> Enable this bit by default for M14K(c) and P5600. There are potentially
> other cores that support this feature, but I do not have a complete
> list.
>
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
> ---
> target/mips/cpu-defs.c.inc | 3 +++
> target/mips/cpu.c | 6 ++++--
> target/mips/cpu.h | 1 +
> 3 files changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-02-16 8:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 5:17 [PATCH v2 0/4] target/mips: misc microMIPS fixes Marcin Nowakowski
2023-02-16 5:17 ` [PATCH v2 1/4] target/mips: fix JALS32/J32 instruction handling for microMIPS Marcin Nowakowski
2023-02-16 5:17 ` [PATCH v2 2/4] target/mips: fix SWM32 handling for micromips Marcin Nowakowski
2023-02-16 5:17 ` [PATCH v2 3/4] target/mips: implement CP0.Config7.WII bit support Marcin Nowakowski
2023-02-16 8:08 ` Philippe Mathieu-Daudé [this message]
2023-02-16 5:17 ` [PATCH v2 4/4] target/mips: set correct CP0.Config[4, 5] values for M14K(c) Marcin Nowakowski
2023-02-16 8:02 ` [PATCH v2 4/4] target/mips: set correct CP0.Config[4,5] " Philippe Mathieu-Daudé
2023-03-09 13:36 ` [PATCH v2 0/4] target/mips: misc microMIPS fixes Philippe Mathieu-Daudé
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