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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k184-20020a6384c1000000b004fb26a80875sm6737148pgd.22.2023.02.24.11.24.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Feb 2023 11:24:25 -0800 (PST) Message-ID: Date: Fri, 24 Feb 2023 09:24:21 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw Content-Language: en-US To: gaosong , qemu-devel@nongnu.org References: <20221224081633.4185445-1-gaosong@loongson.cn> <20221224081633.4185445-11-gaosong@loongson.cn> <268ef762-fce5-ca47-d5f7-bd60955a3a0f@linaro.org> <1ad204fc-8f7e-0f1c-e8f6-163d11f3880b@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/23/23 21:24, gaosong wrote: > I was wrong, the instruction is to sign-extend the odd or even elements of the vector > before the operation, not to sign-extend the result. > E.g > vaddwev_h_b  vd, vj, vk > vd->H[i] = SignExtend(vj->B[2i])  + SignExtend(vk->B[2i]); > vaddwev_w_h  vd, vj, vk > vd->W[i] = SignExtend(vj->H[2i])  + SignExtend(vk->H[2i]); > vaddwev_d_w  vd, vj, vk > vd->Q[i] = SignExtend(vj->W[2i])  + SignExtend(vk->W[2i]); > vaddwev_q_d  vd, vj, vk > vd->Q[i] = SignExtend(vj->D[2i])  + SignExtend(vk->D[2i]); Ok, good example. > static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) > { >     TCGv_vec t1 = tcg_temp_new_vec_matching(a); >     TCGv_vec t2 = tcg_temp_new_vec_matching(b); > >     int halfbits  =  4 << vece; > >     /* Sign-extend even elements from a */ >     tcg_gen_dupi_vec(vece, t1, MAKE_64BIT_MASK(0, halfbits)); >     tcg_gen_and_vec(vece, a, a, t1); No need to mask off these bits... >     tcg_gen_shli_vec(vece, a, a, halfbits); ... because they shift out here anyway. >     tcg_gen_sari_vec(vece, a, a, halfbits); > >     /* Sign-extend even elements from b */ >     tcg_gen_dupi_vec(vece, t2, MAKE_64BIT_MASK(0, halfbits)); >     tcg_gen_and_vec(vece, b, b, t2); >     tcg_gen_shli_vec(vece, b, b, halfbits); >     tcg_gen_sari_vec(vece,  b, b, halfbits); > >     tcg_gen_add_vec(vece, t, a, b); > >     tcg_temp_free_vec(t1); >     tcg_temp_free_vec(t2); > } Otherwise this looks good. >         { >             .fniv = gen_vaddwev_s, >             .fno = gen_helper_vaddwev_q_d, >             .opt_opc = vecop_list, >             .vece = MO_128 >         }, There are no 128-bit vector operations; you'll need to do this one differently. Presumably just load the two 64-bit elements, sign-extend into 128-bits, add with tcg_gen_add2_i64, and store the two 64-bit elements as output. But that won't fit into the tcg_gen_gvec_3 interface. r~