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([2804:7f0:b401:d47f:6989:b93e:2caa:f174]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-4dfa66fdb81sm7956484137.18.2025.05.20.05.59.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 May 2025 05:59:17 -0700 (PDT) Message-ID: Date: Tue, 20 May 2025 09:59:08 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/22] hw/i386/acpi-build: Turn build_q35_osc_method into a generic method To: Eric Auger , eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, Jonathan.Cameron@huawei.com, philmd@linaro.org References: <20250514170431.2786231-1-eric.auger@redhat.com> <20250514170431.2786231-8-eric.auger@redhat.com> Content-Language: en-US From: Gustavo Romero In-Reply-To: <20250514170431.2786231-8-eric.auger@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::932; envelope-from=gustavo.romero@linaro.org; helo=mail-ua1-x932.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Eric, On 5/14/25 14:00, Eric Auger wrote: > GPEX acpi_dsdt_add_pci_osc() does basically the same as > build_q35_osc_method(). > > Rename build_q35_osc_method() into build_pci_host_bridge_osc_method() > and move it into hw/acpi/aml-build.c. In a subsequent patch we will > use this later in place of acpi_dsdt_add_pci_osc(). > > Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Cheers, Gustavo > --- > include/hw/acpi/aml-build.h | 2 ++ > hw/acpi/aml-build.c | 50 ++++++++++++++++++++++++++++++++++ > hw/i386/acpi-build.c | 54 ++----------------------------------- > 3 files changed, 54 insertions(+), 52 deletions(-) > > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h > index c18f681342..177d60b414 100644 > --- a/include/hw/acpi/aml-build.h > +++ b/include/hw/acpi/aml-build.h > @@ -508,4 +508,6 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, > void build_spcr(GArray *table_data, BIOSLinker *linker, > const AcpiSpcrData *f, const uint8_t rev, > const char *oem_id, const char *oem_table_id, const char *name); > + > +Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug); > #endif > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index f8f93a9f66..ba1dfe0b52 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -2614,3 +2614,53 @@ Aml *aml_i2c_serial_bus_device(uint16_t address, const char *resource_source) > > return var; > } > + > +Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug) > +{ > + Aml *if_ctx; > + Aml *if_ctx2; > + Aml *else_ctx; > + Aml *method; > + Aml *a_cwd1 = aml_name("CDW1"); > + Aml *a_ctrl = aml_local(0); > + > + method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > + aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > + > + if_ctx = aml_if(aml_equal( > + aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); > + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); > + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > + > + aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > + > + /* > + * Always allow native PME, AER (no dependencies) > + * Allow SHPC (PCI bridges can have SHPC controller) > + * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. > + */ > + aml_append(if_ctx, aml_and(a_ctrl, > + aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); > + > + if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > + /* Unknown revision */ > + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); > + aml_append(if_ctx, if_ctx2); > + > + if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); > + /* Capabilities bits were masked */ > + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); > + aml_append(if_ctx, if_ctx2); > + > + /* Update DWORD3 in the buffer */ > + aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); > + aml_append(method, if_ctx); > + > + else_ctx = aml_else(); > + /* Unrecognized UUID */ > + aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); > + aml_append(method, else_ctx); > + > + aml_append(method, aml_return(aml_arg(3))); > + return method; > +} > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index b92765fbd9..41fde88b22 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1111,56 +1111,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) > return dev; > } > > -static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) > -{ > - Aml *if_ctx; > - Aml *if_ctx2; > - Aml *else_ctx; > - Aml *method; > - Aml *a_cwd1 = aml_name("CDW1"); > - Aml *a_ctrl = aml_local(0); > - > - method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > - aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > - > - if_ctx = aml_if(aml_equal( > - aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); > - aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); > - aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); > - > - aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); > - > - /* > - * Always allow native PME, AER (no dependencies) > - * Allow SHPC (PCI bridges can have SHPC controller) > - * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. > - */ > - aml_append(if_ctx, aml_and(a_ctrl, > - aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); > - > - if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > - /* Unknown revision */ > - aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); > - aml_append(if_ctx, if_ctx2); > - > - if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); > - /* Capabilities bits were masked */ > - aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); > - aml_append(if_ctx, if_ctx2); > - > - /* Update DWORD3 in the buffer */ > - aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); > - aml_append(method, if_ctx); > - > - else_ctx = aml_else(); > - /* Unrecognized UUID */ > - aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); > - aml_append(method, else_ctx); > - > - aml_append(method, aml_return(aml_arg(3))); > - return method; > -} > - > static void build_acpi0017(Aml *table) > { > Aml *dev, *scope, *method; > @@ -1231,7 +1181,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); > - aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); > + aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en)); > aml_append(dev, aml_pci_edsm()); > aml_append(sb_scope, dev); > if (mcfg_valid) { > @@ -1353,7 +1303,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > /* Expander bridges do not have ACPI PCI Hot-plug enabled */ > - aml_append(dev, build_q35_osc_method(true)); > + aml_append(dev, build_pci_host_bridge_osc_method(true)); > } else { > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > }