Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi,

On 6/1/22 22:00, Frédéric Pétrot wrote:
> This series of patches provides partial 128-bit support for the riscv
> target architecture, namely RVI and RVM, with minimal csr support.


> Frédéric Pétrot (18):
>    exec/memop: Adding signedness to quad definitions
>    exec/memop: Adding signed quad and octo defines
>    qemu/int128: addition of div/rem 128-bit operations
>    target/riscv: additional macros to check instruction support
>    target/riscv: separation of bitwise logic and arithmetic helpers
>    target/riscv: array for the 64 upper bits of 128-bit registers
>    target/riscv: setup everything for rv64 to support rv128 execution


I see this series has been merged as commit afe33262585, with
332dab68785b describing:

     This patch adds the support of the '-cpu rv128' option to
     qemu-system-riscv64 so that we can indicate that we want to
     run rv128 executables.

     Still, there is no support for 128-bit insns at that stage
     so qemu fails miserably (as expected) if launched with this
     option.

Is this code tested? 3 years passed so I wonder about possible
code bitrot here.

(I reached this code by looking at targets not supporting MTTCG).

>    target/riscv: moving some insns close to similar insns
>    target/riscv: accessors to registers upper part and 128-bit load/store
>    target/riscv: support for 128-bit bitwise instructions
>    target/riscv: support for 128-bit U-type instructions
>    target/riscv: support for 128-bit shift instructions
>    target/riscv: support for 128-bit arithmetic instructions
>    target/riscv: support for 128-bit M extension
>    target/riscv: adding high part of some csrs
>    target/riscv: helper functions to wrap calls to 128-bit csr insns
>    target/riscv: modification of the trans_csrxx for 128-bit support
>    target/riscv: actual functions to realize crs 128-bit insns