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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9a3b83sm2648327f8f.33.2025.03.21.08.08.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Mar 2025 08:08:21 -0700 (PDT) Message-ID: Date: Fri, 21 Mar 2025 16:08:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, fabien.portas@grenoble-inp.org, alistair.francis@wdc.com, Pierrick Bouvier , Anton Johansson References: <20220106210108.138226-1-frederic.petrot@univ-grenoble-alpes.fr> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20220106210108.138226-1-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 6/1/22 22:00, Frédéric Pétrot wrote: > This series of patches provides partial 128-bit support for the riscv > target architecture, namely RVI and RVM, with minimal csr support. > Frédéric Pétrot (18): > exec/memop: Adding signedness to quad definitions > exec/memop: Adding signed quad and octo defines > qemu/int128: addition of div/rem 128-bit operations > target/riscv: additional macros to check instruction support > target/riscv: separation of bitwise logic and arithmetic helpers > target/riscv: array for the 64 upper bits of 128-bit registers > target/riscv: setup everything for rv64 to support rv128 execution I see this series has been merged as commit afe33262585, with 332dab68785b describing: This patch adds the support of the '-cpu rv128' option to qemu-system-riscv64 so that we can indicate that we want to run rv128 executables. Still, there is no support for 128-bit insns at that stage so qemu fails miserably (as expected) if launched with this option. Is this code tested? 3 years passed so I wonder about possible code bitrot here. (I reached this code by looking at targets not supporting MTTCG). > target/riscv: moving some insns close to similar insns > target/riscv: accessors to registers upper part and 128-bit load/store > target/riscv: support for 128-bit bitwise instructions > target/riscv: support for 128-bit U-type instructions > target/riscv: support for 128-bit shift instructions > target/riscv: support for 128-bit arithmetic instructions > target/riscv: support for 128-bit M extension > target/riscv: adding high part of some csrs > target/riscv: helper functions to wrap calls to 128-bit csr insns > target/riscv: modification of the trans_csrxx for 128-bit support > target/riscv: actual functions to realize crs 128-bit insns