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[98.150.199.49]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7642db46f00sm8306446b3a.109.2025.07.29.10.21.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 10:21:31 -0700 (PDT) Message-ID: Date: Tue, 29 Jul 2025 07:21:27 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 46/82] target/arm: Implement FEAT_CHK To: Gustavo Romero , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org References: <20250727080254.83840-1-richard.henderson@linaro.org> <20250727080254.83840-47-richard.henderson@linaro.org> <9209927c-6c5f-4499-a3ef-1f4c70951ad0@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <9209927c-6c5f-4499-a3ef-1f4c70951ad0@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/29/25 06:01, Gustavo Romero wrote: >> +static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a) >> +{ >> +    uint64_t feat_en = 0; >> + >> +    if (s->gcs_en) { >> +        feat_en |= 1 << 0; > > I understand that CHKFEAT is currently only tied to GCS but will cover more features > in the future so we can keep feat_en |= 1 << 0 even if it could gate TCG andi directly > on s->gcs_en and do andi with 0. ok. Yep. > > It's curious that this instruction is tied to x16, it seems easy to use any other > general purpose register to query for the features. That's because the instruction is allocated from HINT space, which means that it executes as a NOP on cpus that don't support FEAT_CHK. The HINT space is limited, and it would be wastefull to allocate 32 such insns, one for each register. r~