From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR
Date: Fri, 25 Oct 2019 16:24:34 -0700 [thread overview]
Message-ID: <c667ad7d7f9a2f89ba6859f01cf4e1adf7710f7d.1572045716.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1572045716.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ++++++
target/riscv/cpu.h | 7 +++++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 7 +++++++
target/riscv/csr.c | 25 +++++++++++++++++++++++++
target/riscv/op_helper.c | 4 ++++
6 files changed, 52 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f75c709e35..03622825f3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -229,6 +229,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", *env->mstatus);
+#ifdef TARGET_RISCV32
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", *env->mstatush);
+#endif
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->vsstatus);
@@ -467,6 +470,9 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
env->mie = &env->mie_novirt;
env->mstatus = &env->mstatus_novirt;
+# ifdef TARGET_RISCV32
+ env->mstatush = &env->mstatush_novirt;
+# endif
#endif
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ea56f9059..b8b731df43 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -127,6 +127,10 @@ struct CPURISCVState {
target_ulong mip;
target_ulong mip_novirt;
+#ifdef TARGET_RISCV32
+ target_ulong *mstatush;
+#endif
+
uint32_t miclaim;
target_ulong *mie;
@@ -154,6 +158,9 @@ struct CPURISCVState {
*/
target_ulong mie_novirt;
target_ulong mstatus_novirt;
+#ifdef TARGET_RISCV32
+ target_ulong mstatush_novirt;
+#endif
/* Hypervisor CSRs */
target_ulong hstatus;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 17d168852c..a2358c4956 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,6 +135,9 @@
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
+/* 32-bit only */
+#define CSR_MSTATUSH 0x310
+
/* Legacy Counter Setup (priv v1.9.1) */
/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
#define CSR_MUCOUNTEREN 0x320
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b3ce345f81..79b2f30876 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -950,10 +950,17 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env)) {
riscv_cpu_swap_hypervisor_regs(env);
}
+#ifdef TARGET_RISCV32
+ *env->mstatush = set_field(*env->mstatush, MSTATUS_MPV,
+ riscv_cpu_virt_enabled(env));
+ *env->mstatush = set_field(*env->mstatush, MSTATUS_MTL,
+ riscv_cpu_force_hs_excep_enabled(env));
+#else
*env->mstatus = set_field(*env->mstatus, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
*env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
riscv_cpu_force_hs_excep_enabled(env));
+#endif
/* Trapping to M mode, virt is disabled */
riscv_cpu_set_virt_enabled(env, 0);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a795a02968..8a093abdb2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -364,6 +364,27 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+#ifdef TARGET_RISCV32
+static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = *env->mstatush;
+ return 0;
+}
+
+static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if ((val ^ *env->mstatush) & (MSTATUS_MPV)) {
+ tlb_flush(env_cpu(env));
+ }
+
+ val &= MSTATUS_MPV | MSTATUS_MTL;
+
+ *env->mstatush = val;
+
+ return 0;
+}
+#endif
+
static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->misa;
@@ -1102,6 +1123,10 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVEC] = { any, read_mtvec, write_mtvec },
[CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
+#if defined(TARGET_RISCV32)
+ [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
+#endif
+
/* Legacy Counter Setup (priv v1.9.1) */
[CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e5128570e6..a0a631d722 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -153,7 +153,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, 0);
+#ifdef TARGET_RISCV32
+ *env->mstatush = set_field(*env->mstatush, MSTATUS_MPV, 0);
+#else
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
+#endif
*env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);
--
2.23.0
next prev parent reply other threads:[~2019-10-25 23:50 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 23:23 [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-10-25 23:23 ` [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-10-25 23:23 ` [PATCH v2 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-10-25 23:23 ` [PATCH v2 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-10-25 23:23 ` [PATCH v2 07/27] target/riscv: Print priv and virt in disas log Alistair Francis
2019-10-25 23:23 ` [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-10-25 23:23 ` [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-10-25 23:23 ` [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-10-25 23:23 ` [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-10-25 23:23 ` [PATCH v2 12/27] target/riscv: Add virtual register swapping function Alistair Francis
2019-10-25 23:23 ` [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-10-25 23:23 ` [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-10-25 23:24 ` [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-10-25 23:24 ` [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-10-25 23:24 ` [PATCH v2 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-10-25 23:24 ` [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-25 23:24 ` [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-25 23:24 ` [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-25 23:24 ` [PATCH v2 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-25 23:24 ` [PATCH v2 24/27] target/riscv: Implement second stage MMU Alistair Francis
2019-10-25 23:24 ` Alistair Francis [this message]
2019-10-25 23:24 ` [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-25 23:24 ` [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
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