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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id d15sm2581162wrv.84.2021.05.21.08.44.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 May 2021 08:44:59 -0700 (PDT) Subject: Re: [PATCH 2/2] hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X To: Bin Meng References: <20210521024224.2277634-1-bmeng.cn@gmail.com> <20210521024224.2277634-2-bmeng.cn@gmail.com> <7feeff48-6fa0-19bf-eb72-09caaba8cdb3@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Fri, 21 May 2021 17:44:58 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.374, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Ruimei Yan , Gerd Hoffmann , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/21/21 3:25 PM, Bin Meng wrote: > On Fri, May 21, 2021 at 8:46 PM Philippe Mathieu-Daudé > wrote: >> >> On 5/21/21 4:42 AM, Bin Meng wrote: >>> From: Ruimei Yan >>> >>> Per xHCI spec v1.2 chapter 4.17.5 page 296: >>> >>> If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP) >>> shall be cleared automatically when the PCI dword write generated >>> by the interrupt assertion is complete. >>> >>> Currently QEMU does not clear the IP flag in the MSI / MSI-X mode. >>> This causes subsequent spurious interrupt to be delivered to guests. >>> To solve this, we change the xhci intr_raise() hook routine to have >>> a bool return value that is passed to its caller (the xhci core), >>> with true indicating that IP should be self-cleared. >>> >>> Fixes: 62c6ae04cf43 ("xhci: Initial xHCI implementation") >>> Fixes: 4c47f800631a ("xhci: add msix support") >>> Signed-off-by: Ruimei Yan >>> [bmeng: move IP clear codes from xhci pci to xhci core] >>> Signed-off-by: Bin Meng >>> --- >>> >>> hw/usb/hcd-xhci.h | 2 +- >>> hw/usb/hcd-xhci-pci.c | 8 +++++--- >>> hw/usb/hcd-xhci-sysbus.c | 4 +++- >>> hw/usb/hcd-xhci.c | 8 ++++++-- >>> 4 files changed, 15 insertions(+), 7 deletions(-) >>> >>> diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h >>> index 7bba361f3b..98f598382a 100644 >>> --- a/hw/usb/hcd-xhci.h >>> +++ b/hw/usb/hcd-xhci.h >>> @@ -194,7 +194,7 @@ typedef struct XHCIState { >>> uint32_t flags; >>> uint32_t max_pstreams_mask; >>> void (*intr_update)(XHCIState *s, int n, bool enable); >>> - void (*intr_raise)(XHCIState *s, int n, bool level); >>> + bool (*intr_raise)(XHCIState *s, int n, bool level); >>> DeviceState *hostOpaque; >>> >>> /* Operational Registers */ >>> diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c >>> index b6acd1790c..e934b1a5b1 100644 >>> --- a/hw/usb/hcd-xhci-pci.c >>> +++ b/hw/usb/hcd-xhci-pci.c >>> @@ -57,7 +57,7 @@ static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) >>> } >>> } >>> >>> -static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) >>> +static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) >>> { >>> XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); >>> PCIDevice *pci_dev = PCI_DEVICE(s); >>> @@ -70,13 +70,15 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) >>> >>> if (msix_enabled(pci_dev) && level) { >>> msix_notify(pci_dev, n); >>> - return; >>> + return true; >>> } >>> >>> if (msi_enabled(pci_dev) && level) { >>> msi_notify(pci_dev, n); >>> - return; >>> + return true; >>> } >>> + >>> + return false; >>> } >> >> Could be simplified as: >> >> if (!level) { >> return false; >> } >> if (msix_enabled(pci_dev)) { >> msix_notify(pci_dev, n); >> } >> if (msi_enabled(pci_dev)) { >> msi_notify(pci_dev, n); >> } >> return true; > > The simplified logic will deliver both interrupts if both msix and msi > are enabled. The previous logic prevents such from happening. Oops you are right :) >> Otherwise, >> Reviewed-by: Philippe Mathieu-Daudé This stands.