From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7qDR-00040I-Aj for qemu-devel@nongnu.org; Tue, 31 May 2016 16:24:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7qDM-0002Fb-9E for qemu-devel@nongnu.org; Tue, 31 May 2016 16:24:40 -0400 Received: from mail-qg0-x244.google.com ([2607:f8b0:400d:c04::244]:35654) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7qDM-0002FW-4s for qemu-devel@nongnu.org; Tue, 31 May 2016 16:24:36 -0400 Received: by mail-qg0-x244.google.com with SMTP id t106so11972136qgt.2 for ; Tue, 31 May 2016 13:24:35 -0700 (PDT) Sender: Richard Henderson References: <20160531183928.29406-1-bobby.prani@gmail.com> <20160531183928.29406-2-bobby.prani@gmail.com> From: Richard Henderson Message-ID: Date: Tue, 31 May 2016 13:24:32 -0700 MIME-Version: 1.0 In-Reply-To: <20160531183928.29406-2-bobby.prani@gmail.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pranith Kumar , "open list:All patches CC here" Cc: alex.bennee@linaro.org, serge.fdrv@linaro.org On 05/31/2016 11:39 AM, Pranith Kumar wrote: > +********* Memory Barrier support > + > +* mb <$arg> Document what $arg should be. > +Generate a target memory barrier instruction to ensure memory ordering as being > +enforced by a corresponding guest memory barrier instruction. The ordering > +enforced by the backend may be stricter than the ordering required by the guest. > +It cannot be weaker. This opcode takes an optional constant argument if required > +to generate the appropriate barrier instruction. The backend should take care to The argument is *not* optional. > +void tcg_gen_mb(TCGArg a) > +{ > + /* ??? Enable only when MTTCG is enabled. */ > + tcg_gen_op1(&tcg_ctx, INDEX_op_mb, 0); Pass A to tcg_gen_op1, not 0. > +/* TCGOpmb args */ > +#define TCG_MB_FULL ((TCGArg)(0)) > +#define TCG_MB_READ ((TCGArg)(1)) > +#define TCG_MB_WRITE ((TCGArg)(2)) > +#define TCG_MB_ACQUIRE ((TCGArg)(3)) > +#define TCG_MB_RELEASE ((TCGArg)(4)) This is, IMO, confused. Either we should use the C++11 barrier types, or the Linux barrier types, but not both. r~