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[88.21.102.131]) by smtp.gmail.com with ESMTPSA id f19sm34911739wrf.23.2019.11.20.08.32.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Nov 2019 08:32:46 -0800 (PST) Subject: Re: [PATCH v4 30/37] cris: improve passing PIC interrupt vector to the CPU To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org References: <20191120152442.26657-1-marcandre.lureau@redhat.com> <20191120152442.26657-31-marcandre.lureau@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Wed, 20 Nov 2019 17:32:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191120152442.26657-31-marcandre.lureau@redhat.com> Content-Language: en-US X-MC-Unique: 0LCW-HQYPdSd3adA-sSNBw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/20/19 4:24 PM, Marc-Andr=C3=A9 Lureau wrote: > Instead of accessing cpu interrupt vector directly from PIC, send the > vector value over the qemu_irq. >=20 > Suggested-by: Peter Maydell > Signed-off-by: Marc-Andr=C3=A9 Lureau > Reviewed-by: Peter Maydell > --- > hw/cris/axis_dev88.c | 4 ---- > hw/intc/etraxfs_pic.c | 26 +------------------------- > target/cris/cpu.c | 8 ++++++++ > target/cris/cpu.h | 1 + > 4 files changed, 10 insertions(+), 29 deletions(-) >=20 > diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c > index 940c7dd122..be7760476a 100644 > --- a/hw/cris/axis_dev88.c > +++ b/hw/cris/axis_dev88.c > @@ -253,7 +253,6 @@ void axisdev88_init(MachineState *machine) > const char *kernel_filename =3D machine->kernel_filename; > const char *kernel_cmdline =3D machine->kernel_cmdline; > CRISCPU *cpu; > - CPUCRISState *env; > DeviceState *dev; > SysBusDevice *s; > DriveInfo *nand; > @@ -267,7 +266,6 @@ void axisdev88_init(MachineState *machine) > =20 > /* init CPUs */ > cpu =3D CRIS_CPU(cpu_create(machine->cpu_type)); > - env =3D &cpu->env; > =20 > /* allocate RAM */ > memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram= ", > @@ -297,8 +295,6 @@ void axisdev88_init(MachineState *machine) > =20 > =20 > dev =3D qdev_create(NULL, "etraxfs,pic"); > - /* FIXME: Is there a proper way to signal vectors to the CPU core? = */ > - qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector); > qdev_init_nofail(dev); > s =3D SYS_BUS_DEVICE(dev); > sysbus_mmio_map(s, 0, 0x3001c000); > diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c > index 77f652acec..12988c7aa9 100644 > --- a/hw/intc/etraxfs_pic.c > +++ b/hw/intc/etraxfs_pic.c > @@ -27,8 +27,6 @@ > #include "qemu/module.h" > #include "hw/irq.h" > #include "hw/qdev-properties.h" > -//#include "pc.h" > -//#include "etraxfs.h" > =20 > #define D(x) > =20 > @@ -48,7 +46,6 @@ struct etrax_pic > SysBusDevice parent_obj; > =20 > MemoryRegion mmio; > - void *interrupt_vector; > qemu_irq parent_irq; > qemu_irq parent_nmi; > uint32_t regs[R_MAX]; > @@ -79,11 +76,7 @@ static void pic_update(struct etrax_pic *fs) > } > } > =20 > - if (fs->interrupt_vector) { > - /* hack alert: ptr property */ > - *(uint32_t*)(fs->interrupt_vector) =3D vector; > - } > - qemu_set_irq(fs->parent_irq, !!vector); > + qemu_set_irq(fs->parent_irq, vector); > } > =20 > static uint64_t > @@ -163,28 +156,11 @@ static void etraxfs_pic_init(Object *obj) > sysbus_init_mmio(sbd, &s->mmio); > } > =20 > -static Property etraxfs_pic_properties[] =3D { > - DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vect= or), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > -static void etraxfs_pic_class_init(ObjectClass *klass, void *data) > -{ > - DeviceClass *dc =3D DEVICE_CLASS(klass); > - > - dc->props =3D etraxfs_pic_properties; > - /* > - * Note: pointer property "interrupt_vector" may remain null, thus > - * no need for dc->user_creatable =3D false; > - */ > -} > - > static const TypeInfo etraxfs_pic_info =3D { > .name =3D TYPE_ETRAX_FS_PIC, > .parent =3D TYPE_SYS_BUS_DEVICE, > .instance_size =3D sizeof(struct etrax_pic), > .instance_init =3D etraxfs_pic_init, > - .class_init =3D etraxfs_pic_class_init, > }; > =20 > static void etraxfs_pic_register_types(void) > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index 7adfd6caf4..6a857f548d 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -147,6 +147,14 @@ static void cris_cpu_set_irq(void *opaque, int irq, = int level) > CPUState *cs =3D CPU(cpu); > int type =3D irq =3D=3D CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INT= ERRUPT_NMI; > =20 > + if (irq =3D=3D CRIS_CPU_IRQ) { > + /* > + * The PIC passes us the vector for the IRQ as the value it send= s > + * over the qemu_irq line > + */ > + cpu->env.interrupt_vector =3D level; I worked on a series that change level to a boolean, but having a way to=20 pass a vectored IRQ via the IRQ API seems useful. Maybe we should clarify the qemu_irq_handler prototype documentation.=20 Unfortunately it is declared in "qemu/typedefs.h", and the documentation=20 is expected in "hw/irq.h". Reviewed-by: Philippe Mathieu-Daud=C3=A9 > + } > + > if (level) { > cpu_interrupt(cs, type); > } else { > diff --git a/target/cris/cpu.h b/target/cris/cpu.h > index aba0a66474..a7c2a8e15b 100644 > --- a/target/cris/cpu.h > +++ b/target/cris/cpu.h > @@ -34,6 +34,7 @@ > #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 > =20 > /* CRUS CPU device objects interrupt lines. */ > +/* PIC passes the vector for the IRQ as the value of it sends over qemu_= irq */ > #define CRIS_CPU_IRQ 0 > #define CRIS_CPU_NMI 1 > =20 >=20