From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
alistair23@gmail.com, chihmin.chao@sifive.com,
palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line
Date: Sat, 4 Jan 2020 10:08:21 +1100 [thread overview]
Message-ID: <c6ca305c-0e80-f690-a299-bbf4ebdbfbca@linaro.org> (raw)
In-Reply-To: <20200103033347.20909-3-zhiwei_liu@c-sky.com>
On 1/3/20 2:33 PM, LIU Zhiwei wrote:
> + if (cpu->cfg.ext_v) {
> + target_misa |= RVV;
> + if (!is_power_of_2(cpu->cfg.vlen)) {
> + error_setg(errp,
> + "Vector extension VLEN must be power of 2");
> + return;
> + }
> + if (cpu->cfg.vlen > RV_VLEN_MAX) {
> + error_setg(errp,
> + "Vector extension VLEN must <= %d", RV_VLEN_MAX);
> + return;
> + }
> + if (!is_power_of_2(cpu->cfg.elen)) {
> + error_setg(errp,
> + "Vector extension ELEN must be power of 2");
> + return;
> + }
Missing maximum on elen.
Missing minimum on vlen, which, as I discussed earlier, should be 128 to avoid
asserts in tcg-op-gvec.c.
> #define PRIV_VERSION_1_10_0 0x00011000
> #define PRIV_VERSION_1_11_0 0x00011100
>
> +#define VEXT_VERSION_0_07_1 0x00000071
To match the other version number formats, surely this should be 0x00000701.
r~
next prev parent reply other threads:[~2020-01-03 23:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-03 3:33 [PATCH v3 0/4] RISC-V: support vector extension part 1 LIU Zhiwei
2020-01-03 3:33 ` [PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState LIU Zhiwei
2020-01-03 23:05 ` Richard Henderson
2020-01-03 3:33 ` [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line LIU Zhiwei
2020-01-03 23:08 ` Richard Henderson [this message]
2020-01-06 21:48 ` Jim Wilson
2020-01-07 1:42 ` LIU Zhiwei
2020-01-03 3:33 ` [PATCH v3 3/4] RISC-V: support vector extension csr LIU Zhiwei
2020-01-03 23:14 ` Richard Henderson
2020-01-06 22:00 ` Jim Wilson
2020-01-07 1:34 ` LIU Zhiwei
2020-01-03 3:33 ` [PATCH v3 4/4] RISC-V: add vector extension configure instruction LIU Zhiwei
2020-01-03 23:41 ` Richard Henderson
2020-01-07 2:11 ` LIU Zhiwei
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