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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 26 Feb 2019 09:14:02 -0800
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Subject: Re: [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI
 instruction PEXCW
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To: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>, qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net

On 2/26/19 4:23 AM, Mateja Marjanovic wrote:
> +    } else if (rt == rd) {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 32) - 1;
> +        uint64_t mask1 = mask0 << 32;
> +
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> +        tcg_gen_shri_i64(t0, t0, 32);
> +        tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> +        tcg_gen_shli_i64(t1, t1, 32);
> +
> +        tcg_gen_and_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
> +        tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +
> +        tcg_gen_and_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
> +        tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    } else {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 32) - 1;
> +        uint64_t mask1 = mask0 << 32;
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> +        tcg_gen_shri_i64(t1, t1, 32);
> +        tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
> +
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> +        tcg_gen_shli_i64(t0, t0, 32);
> +        tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> +        tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
> +
> +        tcg_temp_free(t0);
> +        tcg_temp_free(t1);
> +    }

Likewise, why are you duplicating cases?

Also, this can be simplified with deposit:

    tcg_gen_shri_i64(t0, cpu_gpr[rt], 32);
    tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmu[rt], 32, 32);
    tcg_gen_deposit_i64(cpu_mmu[rd], cpu_mmu[rt], t0, 0, 32);


r~