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Thu, 28 Nov 2024 09:49:05 -0800 (PST) Received: from [172.20.3.167] ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b68492114bsm75498985a.9.2024.11.28.09.49.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Nov 2024 09:49:04 -0800 (PST) Message-ID: Date: Thu, 28 Nov 2024 11:49:01 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-10.0 14/25] softfloat: Allow runtime choice of NaN propagation for muladd To: Peter Maydell , qemu-devel@nongnu.org References: <20241128104310.3452934-1-peter.maydell@linaro.org> <20241128104310.3452934-15-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241128104310.3452934-15-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/28/24 04:42, Peter Maydell wrote: > +/* > + * 3-input NaN propagation rule, for fused multiply-add. Individual > + * architectures have different rules for which input NaN is > + * propagated to the output when there is more than one NaN on the > + * input. > + * > + * If default_nan_mode is enabled then it is valid not to set a NaN > + * propagation rule, because the softfloat code guarantees not to try > + * to pick a NaN to propagate in default NaN mode. When not in > + * default-NaN mode, it is an error for the target not to set the rule > + * in float_status if it uses a muladd, and we will assert if we need > + * to handle an input NaN and no rule was selected. > + * > + * For QEMU, the multiply-add operation is A * B + C. > + * > + * NB: we don't list all 12 possibilities here or implement them > + * in pickNaNMulAdd; if your architecture needs one of the missing > + * combinations you should add it. > + */ > +typedef enum __attribute__((__packed__)) { > + /* No propagation rule specified */ > + float_3nan_prop_none = 0, > + /* Prefer SNaN over QNaN, then operand A over B over C */ > + float_3nan_prop_s_abc, > + /* Prefer SNaN over QNaN, then operand C over A over B */ > + float_3nan_prop_s_cab, > + /* Prefer SNaN over QNaN, then operand C over B over A */ > + float_3nan_prop_s_cba, > + /* Prefer A over B over C regardless of SNaN vs QNaN */ > + float_3nan_prop_abc, > + /* Prefer A over C over B regardless of SNaN vs QNaN */ > + float_3nan_prop_acb, > + /* Prefer C over B over A regardless of SNaN vs QNaN */ > + float_3nan_prop_cba, > +} Float3NaNPropRule; Oof. I was imagining a bit more data driven solution, rather than explicitly enumerating. For instance: FIELD(3NAN, 1ST, 0, 2) FIELD(3NAN, 2ND, 2, 2) FIELD(3NAN, 3RD, 4, 2) FIELD(3NAN, SNAN, 6, 1) float_3nan_prop_abc = (0 << R_3NAN_1ST_SHIFT) | (1 << R_3NAN_2ND_SHIFT) | (2 << R_3NAN_3RD_SHIFT), float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, FloatClass cls[3] = { a_cls, b_cls, c_cls }; if (rule & R_3NAN_SNAN_MASK && abc_mask & float_cmask_snan) { do { which = rule & R_3NAN_1ST_MASK; rule >>= R_3NAN_1ST_LENGTH; } while (!is_snan(cls[which])); } else { do { which = rule & R_3NAN_1ST_MASK; rule >>= R_3NAN_1ST_LENGTH; } while (!is_nan(cls[which])); } return which; r~