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[176.184.13.61]) by smtp.gmail.com with ESMTPSA id r22-20020a170906351600b00a0c01560bdfsm3835090eja.139.2023.11.28.02.03.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Nov 2023 02:03:33 -0800 (PST) Message-ID: Date: Tue, 28 Nov 2023 11:03:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-9.0 v2 4/8] target/riscv/cpu.c: add riscv_cpu_is_32bit() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com References: <20231127113752.1290265-1-dbarboza@ventanamicro.com> <20231127113752.1290265-5-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20231127113752.1290265-5-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 27/11/23 12:37, Daniel Henrique Barboza wrote: > Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit. > The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check > the first CPU of a given hart array, not any given CPU. > > Create a helper to retrieve the info for any given CPU, not the first > CPU of the hart array. The helper is using the same 32 bit check that > riscv_cpu_satp_mode_finalize() was doing. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones > --- > target/riscv/cpu.c | 7 ++++++- > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé