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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2025 03:59:10.6185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53126bab-3c4f-49d6-677c-08dd968982eb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7272 Received-SPF: permerror client-ip=40.107.220.76; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.13, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/16/2025 8:13 PM, Philippe Mathieu-Daudé wrote: > On 16/5/25 12:05, Sairaj Kodilkar wrote: >> Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode") >> introduces the support for "pt" flag by enabling nodma memory when >> "pt=off". This allowed VFIO devices to successfully register notifiers >> by using nodma region. >> >> But, This also broke things when guest is booted with the iommu=nopt >> because, devices bypass the IOMMU and use untranslated addresses >> (IOVA) to >> perform DMA reads/writes to the nodma memory region, ultimately >> resulting in >> a failure to setup the devices in the guest. >> >> Fix the above issue by always enabling the amdvi_dev_as->iommu memory >> region. >> But this will once again cause VFIO devices to fail while registering the >> notifiers with AMD IOMMU memory region. >> >> Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode") >> Signed-off-by: Sairaj Kodilkar >> Reviewed-by: Vasant Hegde >> --- >>   hw/i386/amd_iommu.c | 12 ++---------- >>   1 file changed, 2 insertions(+), 10 deletions(-) >> >> diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c >> index 5f9b95279997..df8ba5d39ada 100644 >> --- a/hw/i386/amd_iommu.c >> +++ b/hw/i386/amd_iommu.c >> @@ -1426,7 +1426,6 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus >> *bus, void *opaque, int devfn) >>       AMDVIState *s = opaque; >>       AMDVIAddressSpace **iommu_as, *amdvi_dev_as; >>       int bus_num = pci_bus_num(bus); >> -    X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); >>       iommu_as = s->address_spaces[bus_num]; >> @@ -1486,15 +1485,8 @@ static AddressSpace >> *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) >>                                               AMDVI_INT_ADDR_FIRST, >>                                               &amdvi_dev_as->iommu_ir, >> 1); >> -        if (!x86_iommu->pt_supported) { >> -            memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, >> false); >> -            memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as- >> >iommu), >> -                                      true); >> -        } else { >> -            memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as- >> >iommu), >> -                                      false); >> -            memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); >> -        } >> +        memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); > > I have no clue about this device but wonder what is the usefulness of > iommu_nodma now, isn't it dead code? > Hi Philippe, Indeed the iommu_nodma is dead. The reason I did not remove the iommu_nodma region completely is that, Alejandro's DMA remapping patches [1] uses this region to dynamically switch the address space. [1] https://lore.kernel.org/qemu-devel/20250502021605.1795985-1-alejandro.j.jimenez@oracle.com/ Thanks Sairaj >> +        memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as- >> >iommu), true); >>       } >>       return &iommu_as[devfn]->as; >>   } >