From: Thomas Huth <thuth@redhat.com>
To: Iris Chen <irischenlj@fb.com>, qemu-devel@nongnu.org
Cc: pdel@fb.com, qemu-arm@nongnu.org, clg@kaod.org,
patrick@stwcx.xyz, alistair@alistair23.me, kwolf@redhat.com,
hreitz@redhat.com, peter.maydell@linaro.org, andrew@aj.id.au,
joel@jms.id.au, lvivier@redhat.com, pbonzini@redhat.com,
qemu-block@nongnu.org
Subject: Re: [PATCH v2 2/2] hw: m25p80: add tests for write protect
Date: Thu, 9 Jun 2022 08:24:58 +0200 [thread overview]
Message-ID: <c7a83cff-c215-9c2e-0a88-956c67742f2d@redhat.com> (raw)
In-Reply-To: <20220609031320.2212468-2-irischenlj@fb.com>
On 09/06/2022 05.13, Iris Chen wrote:
> Signed-off-by: Iris Chen <irischenlj@fb.com>
> ---
> Include the tests in a separate patch. Using qtest_set_irq_in() as per review.
>
> tests/qtest/aspeed_smc-test.c | 60 +++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
> index c5d97d4410..7786addfb8 100644
> --- a/tests/qtest/aspeed_smc-test.c
> +++ b/tests/qtest/aspeed_smc-test.c
> @@ -392,6 +392,64 @@ static void test_read_status_reg(void)
> flash_reset();
> }
>
> +static void test_status_reg_write_protection(void)
> +{
> + uint8_t r;
> +
> + spi_conf(CONF_ENABLE_W0);
> +
> + /* default case: WP# is high and SRWD is low -> status register writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, SRWD);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + /* WP# high and SRWD high -> status register writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, 0);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, 0);
> +
> + /* WP# low and SRWD low -> status register writable */
> + qtest_set_irq_in(global_qtest,
> + "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, SRWD);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + /* WP# low and SRWD high -> status register NOT writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, 0);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + /* write is not successful */
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + qtest_set_irq_in(global_qtest,
> + "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
> + flash_reset();
> +}
FWIW, I'd prefer if we could use qtest_writeb / qtest_readb for new code
instead of writeb / readb, but well, the whole file is already written that
way, so this is only "consistent" ... so:
Acked-by: Thomas Huth <thuth@redhat.com>
next prev parent reply other threads:[~2022-06-09 6:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 3:13 [PATCH v2 1/2] hw: m25p80: add WP# pin and SRWD bit for write protection Iris Chen
2022-06-09 3:13 ` [PATCH v2 2/2] hw: m25p80: add tests for write protect Iris Chen
2022-06-09 6:24 ` Thomas Huth [this message]
2022-06-09 11:32 ` [PATCH v2 1/2] hw: m25p80: add WP# pin and SRWD bit for write protection Cédric Le Goater
2022-06-09 19:22 ` Francisco Iglesias
2022-06-09 20:06 ` Peter Delevoryas
2022-06-14 5:45 ` Dan Zhang
2022-06-14 6:19 ` Dan Zhang
2022-06-14 7:13 ` Cédric Le Goater
2022-06-14 16:02 ` [PATCH] hw:w25p80: Add STATE_STANDBY to handle incorrect command Dan Zhang
2022-06-14 17:15 ` Dan Zhang
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