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[176.184.46.22]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3048b93asm4502082a12.56.2024.06.24.00.48.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jun 2024 00:48:12 -0700 (PDT) Message-ID: Date: Mon, 24 Jun 2024 09:48:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/9] target/arm: Factor out code for setting MTE TCF0 field To: Gustavo Romero , qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: peter.maydell@linaro.org References: <20240624053046.221802-1-gustavo.romero@linaro.org> <20240624053046.221802-7-gustavo.romero@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240624053046.221802-7-gustavo.romero@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 24/6/24 07:30, Gustavo Romero wrote: > Factor out the code used for setting the MTE TCF0 field from the prctl > code into a convenient function. Other subsystems, like gdbstub, need to > set this field as well, so keep it as a separate function to avoid > duplication and ensure consistency in how this field is set across the > board. > > Signed-off-by: Gustavo Romero > --- > linux-user/aarch64/mte_user_helper.h | 38 ++++++++++++++++++++++++++++ > linux-user/aarch64/target_prctl.h | 22 ++-------------- > 2 files changed, 40 insertions(+), 20 deletions(-) > create mode 100644 linux-user/aarch64/mte_user_helper.h > > diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_user_helper.h > new file mode 100644 > index 0000000000..fd92e71c00 > --- /dev/null > +++ b/linux-user/aarch64/mte_user_helper.h > @@ -0,0 +1,38 @@ > +/* > + * ARM MemTag convenience functions. > + * > + * This code is licensed under the GNU GPL v2 or later. > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later > + */ > + > +#ifndef MTE_H > +#define MTE_H > + > +#include "sys/prctl.h" > + > +static inline void arm_set_mte_tcf0(CPUArchState *env, abi_long value) > +{ > + /* > + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. > + * > + * The kernel has a per-cpu configuration for the sysadmin, > + * /sys/devices/system/cpu/cpu/mte_tcf_preferred, > + * which qemu does not implement. > + * > + * Because there is no performance difference between the modes, and > + * because SYNC is most useful for debugging MTE errors, choose SYNC > + * as the preferred mode. With this preference, and the way the API > + * uses only two bits, there is no way for the program to select > + * ASYMM mode. > + */ > + unsigned tcf = 0; > + if (value & PR_MTE_TCF_SYNC) { > + tcf = 1; > + } else if (value & PR_MTE_TCF_ASYNC) { > + tcf = 2; > + } > + env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); Missing "qemu/bitops.h" header. > +} > + > +#endif /* MTE_H */ > diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h > index aa8e203c15..ed75b9e4b5 100644 > --- a/linux-user/aarch64/target_prctl.h > +++ b/linux-user/aarch64/target_prctl.h > @@ -7,6 +7,7 @@ > #define AARCH64_TARGET_PRCTL_H > > #include "target/arm/cpu-features.h" > +#include "mte_user_helper.h" > > static abi_long do_prctl_sve_get_vl(CPUArchState *env) > { > @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) > env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; > > if (cpu_isar_feature(aa64_mte, cpu)) { > - /* > - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. > - * > - * The kernel has a per-cpu configuration for the sysadmin, > - * /sys/devices/system/cpu/cpu/mte_tcf_preferred, > - * which qemu does not implement. > - * > - * Because there is no performance difference between the modes, and > - * because SYNC is most useful for debugging MTE errors, choose SYNC > - * as the preferred mode. With this preference, and the way the API > - * uses only two bits, there is no way for the program to select > - * ASYMM mode. > - */ > - unsigned tcf = 0; > - if (arg2 & PR_MTE_TCF_SYNC) { > - tcf = 1; > - } else if (arg2 & PR_MTE_TCF_ASYNC) { > - tcf = 2; > - } > - env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); > + arm_set_mte_tcf0(env, arg2); > > /* > * Write PR_MTE_TAG to GCR_EL1[Exclude].