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[174.21.138.234]) by smtp.gmail.com with ESMTPSA id d71sm2616691pfd.46.2020.03.26.16.32.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Mar 2020 16:32:09 -0700 (PDT) Subject: Re: [PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> From: Richard Henderson Message-ID: Date: Thu, 26 Mar 2020 16:32:07 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/26/20 3:44 PM, Alistair Francis wrote: > Take the result of stage-1 and stage-2 page table walks and AND the two > protection flags together. This way we require both to set permissions > instead of just stage-2. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu_helper.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index f36d184b7b..50e13a064f 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > #ifndef CONFIG_USER_ONLY > vaddr im_address; > hwaddr pa = 0; > - int prot; > + int prot, prot2; > bool pmp_violation = false; > bool m_mode_two_stage = false; > bool hs_mode_two_stage = false; > @@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > /* Second stage lookup */ > im_address = pa; > > - ret = get_physical_address(env, &pa, &prot, im_address, > + ret = get_physical_address(env, &pa, &prot2, im_address, > access_type, mmu_idx, false, true); > > qemu_log_mask(CPU_LOG_MMU, > "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " > TARGET_FMT_plx " prot %d\n", > - __func__, im_address, ret, pa, prot); > + __func__, im_address, ret, pa, prot2); > + > + prot &= prot2; > > if (riscv_feature(env, RISCV_FEATURE_PMP) && > (ret == TRANSLATE_SUCCESS) && > Whee! Yes, I think this is what you've been looking for. Reviewed-by: Richard Henderson r~