Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

[Richard Henderson <rth@twiddle.net>]

On 02/01/2017 02:04 AM, Stafford Horne wrote:
> On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote:
>> On 01/26/2017 05:12 AM, Stafford Horne wrote:
>>> I just sent you a mail with a link to my kernel for download.
>>>
>>> One thing I noticed is you passed '-append console=ttyS0' I think that
>>> does nothing on openrisc since as far as I know openrisc only gets boot
>>> params from the device tree file. I tried with and without it and got no
>>> differences.
>>
>> That was just reflex, wondering where the output went.
>>
>>> Another thing, I am using a 'late' version of gcc built with musl cross [1]
>>> , I dont think it would make a difference, but maybe?
>>
>> I think that's likely the difference.  I can indeed boot your kernel.
> 
> Hi Richard,
> 
> For kernel builds I have created toolchain binaries here:
> 
>   http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/
> 
> These should work.
> 
> If all is ok with the qemu patch I sent what is the next step to get them
> incorporated.  Do you need any help from me?
> 
> ... Actually I just checked your branch on github, it looks like you are
> doing a few updates.  Let me know if you want me to review anything.

Yes, I've been attempting to revive a patch set from 2013 that cleans up the
implementation, fixing a few other bugs in the process.

However, testing it properly has been tricky.  It appears as if I'm debugging
qemu and gcc simultaneously, while your gdb branch doesn't want to compile for
me.  So I've been limited to instruction traces from qemu, which is slow going.

If you'd like to do your own testing on my tgt-or1k-2 branch, that would be
appreciated.


r~