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Tue, 12 Nov 2019 08:45:48 +0100 (CET) Received: from kaod.org (lfbn-1-2229-223.w90-76.abo.wanadoo.fr [90.76.50.223]) (Authenticated sender: clg@kaod.org) by player776.ha.ovh.net (Postfix) with ESMTPSA id 56029BF536AB; Tue, 12 Nov 2019 07:45:43 +0000 (UTC) Subject: Re: [PATCH 2/4] aspeed/scu: Fix W1C behavior To: Joel Stanley , Peter Maydell , Andrew Jeffery References: <20191112064058.13275-1-joel@jms.id.au> <20191112064058.13275-3-joel@jms.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Tue, 12 Nov 2019 08:45:42 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <20191112064058.13275-3-joel@jms.id.au> Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-Ovh-Tracer-Id: 7146086708984253248 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedruddvkedgheejucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdqfffguegfifdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepuffvfhfhkffffgggjggtgfesthekredttdefjeenucfhrhhomhepveorughrihgtpgfnvggpifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpledtrdejiedrhedtrddvvdefnecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejjeeirdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpedt Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.56.233 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/11/2019 07:40, Joel Stanley wrote: > This models the clock write one to clear registers, and fixes up some > incorrect behavior in all of the write to clear registers. >=20 > There was also a typo in one of the register definitions. >=20 > Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater > --- > hw/misc/aspeed_scu.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 717509bc5460..aac4645f8c3c 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -98,7 +98,7 @@ > #define AST2600_CLK_STOP_CTRL TO_REG(0x80) > #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) > #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) > -#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) > +#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) > #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) > #define AST2600_HPLL_PARAM TO_REG(0x200) > #define AST2600_HPLL_EXT TO_REG(0x204) > @@ -532,11 +532,12 @@ static uint64_t aspeed_ast2600_scu_read(void *opa= que, hwaddr offset, > return s->regs[reg]; > } > =20 > -static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint= 64_t data, > +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint= 64_t data64, > unsigned size) > { > AspeedSCUState *s =3D ASPEED_SCU(opaque); > int reg =3D TO_REG(offset); > + uint32_t data =3D data64; > =20 > if (reg >=3D ASPEED_AST2600_SCU_NR_REGS) { > qemu_log_mask(LOG_GUEST_ERROR, > @@ -563,15 +564,19 @@ static void aspeed_ast2600_scu_write(void *opaque= , hwaddr offset, uint64_t data, > /* fall through */ > case AST2600_SYS_RST_CTRL: > case AST2600_SYS_RST_CTRL2: > + case AST2600_CLK_STOP_CTRL: > + case AST2600_CLK_STOP_CTRL2: > /* W1S (Write 1 to set) registers */ > s->regs[reg] |=3D data; > return; > case AST2600_SYS_RST_CTRL_CLR: > case AST2600_SYS_RST_CTRL2_CLR: > + case AST2600_CLK_STOP_CTRL_CLR: > + case AST2600_CLK_STOP_CTRL2_CLR: > case AST2600_HW_STRAP1_CLR: > case AST2600_HW_STRAP2_CLR: > /* W1C (Write 1 to clear) registers */ > - s->regs[reg] &=3D ~data; > + s->regs[reg - 1] &=3D ~data; > return; > =20 > case AST2600_RNG_DATA: >=20