From: WANG Xuerui <i.qemu@xen0n.name>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: git@xen0n.name
Subject: Re: [PATCH v2 02/10] target/loongarch: Disassemble jirl properly
Date: Sun, 22 Jan 2023 16:24:12 +0800 [thread overview]
Message-ID: <c87e5b2d-3923-d7af-7e5e-ec994bd93cec@xen0n.name> (raw)
In-Reply-To: <20230118011123.392823-3-richard.henderson@linaro.org>
On 1/18/23 09:11, Richard Henderson wrote:
> While jirl shares the same instruction format as bne etc,
> it is not assembled the same. In particular, rd is printed
> first not second and the immediate is not pc-relative.
>
> Decode into the arg_rr_i structure, which prints correctly.
> This changes the "offs" member to "imm", to update translate.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/disas.c | 2 +-
> target/loongarch/insn_trans/trans_branch.c.inc | 2 +-
> target/loongarch/insns.decode | 3 ++-
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
> index 858dfcc53a..7cffd853ec 100644
> --- a/target/loongarch/disas.c
> +++ b/target/loongarch/disas.c
> @@ -628,7 +628,7 @@ INSN(beqz, r_offs)
> INSN(bnez, r_offs)
> INSN(bceqz, c_offs)
> INSN(bcnez, c_offs)
> -INSN(jirl, rr_offs)
> +INSN(jirl, rr_i)
> INSN(b, offs)
> INSN(bl, offs)
> INSN(beq, rr_offs)
> diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
> index 65dbdff41e..a860f7e733 100644
> --- a/target/loongarch/insn_trans/trans_branch.c.inc
> +++ b/target/loongarch/insn_trans/trans_branch.c.inc
> @@ -23,7 +23,7 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
> TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
>
> - tcg_gen_addi_tl(cpu_pc, src1, a->offs);
> + tcg_gen_addi_tl(cpu_pc, src1, a->imm);
> tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
> gen_set_gpr(a->rd, dest, EXT_NONE);
> tcg_gen_lookup_and_goto_ptr();
> diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
> index 3fdc6e148c..de7b8f0f3c 100644
> --- a/target/loongarch/insns.decode
> +++ b/target/loongarch/insns.decode
> @@ -67,6 +67,7 @@
> @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
> @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
> @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
> +@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
> @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
> @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
> @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
> @@ -444,7 +445,7 @@ beqz 0100 00 ................ ..... ..... @r_offs21
> bnez 0100 01 ................ ..... ..... @r_offs21
> bceqz 0100 10 ................ 00 ... ..... @c_offs21
> bcnez 0100 10 ................ 01 ... ..... @c_offs21
> -jirl 0100 11 ................ ..... ..... @rr_offs16
> +jirl 0100 11 ................ ..... ..... @rr_i16s2
> b 0101 00 .......................... @offs26
> bl 0101 01 .......................... @offs26
> beq 0101 10 ................ ..... ..... @rr_offs16
Reviewed-by: WANG Xuerui <git@xen0n.name>
Thanks for the catch!
next prev parent reply other threads:[~2023-01-22 8:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-18 1:11 [PATCH v2 00/10] tcg/loongarch64: Reorg goto_tb and cleanups Richard Henderson
2023-01-18 1:11 ` [PATCH v2 01/10] target/loongarch: Enable the disassembler for host tcg Richard Henderson
2023-01-22 8:32 ` WANG Xuerui
2023-01-23 8:37 ` Philippe Mathieu-Daudé
2023-01-18 1:11 ` [PATCH v2 02/10] target/loongarch: Disassemble jirl properly Richard Henderson
2023-01-22 8:24 ` WANG Xuerui [this message]
2023-01-18 1:11 ` [PATCH v2 03/10] target/loongarch: Disassemble pcadd* addresses Richard Henderson
2023-01-22 8:24 ` WANG Xuerui
2023-01-18 1:11 ` [PATCH v2 04/10] tcg/loongarch64: Optimize immediate loading Richard Henderson
2023-01-22 8:21 ` WANG Xuerui
2023-01-18 1:11 ` [PATCH v2 05/10] tcg/loongarch64: Update tcg-insn-defs.c.inc Richard Henderson
2023-01-22 8:20 ` WANG Xuerui
2023-01-23 8:33 ` Philippe Mathieu-Daudé
2023-01-18 1:11 ` [PATCH v2 06/10] tcg/loongarch64: Introduce tcg_out_addi Richard Henderson
2023-01-23 6:52 ` WANG Xuerui
2023-01-18 1:11 ` [PATCH v2 07/10] tcg/loongarch64: Improve setcond expansion Richard Henderson
2023-01-23 7:10 ` WANG Xuerui
2023-01-18 1:11 ` [PATCH v2 08/10] tcg/loongarch64: Implement movcond Richard Henderson
2023-01-22 8:23 ` WANG Xuerui
2023-01-18 1:11 ` [PATCH v2 09/10] tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst Richard Henderson
2023-01-22 8:22 ` WANG Xuerui
2023-01-23 8:32 ` Philippe Mathieu-Daudé
2023-01-18 1:11 ` [PATCH v2 10/10] tcg/loongarch64: Reorg goto_tb implementation Richard Henderson
2023-01-23 8:12 ` WANG Xuerui
2023-01-22 8:28 ` [PATCH v2 00/10] tcg/loongarch64: Reorg goto_tb and cleanups WANG Xuerui
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