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From: Paolo Bonzini <pbonzini@redhat.com>
To: Magnus Kulke <magnuskulke@linux.microsoft.com>,
	magnuskulke@microsoft.com, qemu-devel@nongnu.org,
	liuwe@microsoft.com
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	"Wei Liu" <wei.liu@kernel.org>,
	"Phil Dennis-Jordan" <phil@philjordan.eu>,
	"Roman Bolshakov" <rbolshakov@ddn.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Zhao Liu" <zhao1.liu@intel.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Cameron Esfahani" <dirty@apple.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Daniel P. Berrangé" <berrange@redhat.com>
Subject: Re: [RFC PATCH 02/25] target/i386/emulate: allow instruction decoding from stream
Date: Tue, 20 May 2025 14:42:07 +0200	[thread overview]
Message-ID: <c8a8971e-5cf6-4a13-a01b-1d3cd25fd0fb@redhat.com> (raw)
In-Reply-To: <20250520113018.49569-3-magnuskulke@linux.microsoft.com>

On 5/20/25 13:29, Magnus Kulke wrote:
> Introduce a new helper function to decode x86 instructions from a
> raw instruction byte stream. MSHV delivers an instruction stream in a
> buffer of the vm_exit message. It can be used to speed up MMIO
> emulation, since instructions do not have to be fetched and translated.
> 
> Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>

Missing update of hvf_x86_emul_ops.

Paolo

> ---
>   target/i386/emulate/x86_decode.c | 32 +++++++++++++++++++++++++++-----
>   target/i386/emulate/x86_decode.h | 11 +++++++++++
>   target/i386/emulate/x86_emu.c    |  3 ++-
>   target/i386/emulate/x86_emu.h    |  1 +
>   4 files changed, 41 insertions(+), 6 deletions(-)
> 
> diff --git a/target/i386/emulate/x86_decode.c b/target/i386/emulate/x86_decode.c
> index 88be9479a8..7a862b976e 100644
> --- a/target/i386/emulate/x86_decode.c
> +++ b/target/i386/emulate/x86_decode.c
> @@ -60,6 +60,7 @@ static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
>                                       int size)
>   {
>       uint64_t val = 0;
> +    target_ulong va;
>   
>       switch (size) {
>       case 1:
> @@ -71,10 +72,16 @@ static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
>           VM_PANIC_EX("%s invalid size %d\n", __func__, size);
>           break;
>       }
> -    target_ulong va  = linear_rip(env_cpu(env), env->eip) + decode->len;
> -    emul_ops->read_mem(env_cpu(env), &val, va, size);
> +
> +	/* copy the bytes from the instruction stream, if available */
> +	if (decode->stream && decode->len + size <= decode->stream->len) {
> +		memcpy(&val, decode->stream->bytes + decode->len, size);
> +	} else {
> +		va = linear_rip(env_cpu(env), env->eip) + decode->len;
> +		emul_ops->fetch_instruction(env_cpu(env), &val, va, size);
> +	}
>       decode->len += size;
> -
> +
>       return val;
>   }
>   
> @@ -2076,9 +2083,8 @@ static void decode_opcodes(CPUX86State *env, struct x86_decode *decode)
>       }
>   }
>   
> -uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode)
> +static uint32_t decode_opcode(CPUX86State *env, struct x86_decode *decode)
>   {
> -    memset(decode, 0, sizeof(*decode));
>       decode_prefix(env, decode);
>       set_addressing_size(env, decode);
>       set_operand_size(env, decode);
> @@ -2088,6 +2094,22 @@ uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode)
>       return decode->len;
>   }
>   
> +uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode)
> +{
> +	memset(decode, 0, sizeof(*decode));
> +	return decode_opcode(env, decode);
> +}
> +
> +uint32_t decode_instruction_stream(CPUX86State *env, struct x86_decode *decode,
> +		                           struct x86_insn_stream *stream)
> +{
> +	memset(decode, 0, sizeof(*decode));
> +	if (stream != NULL) {
> +		decode->stream = stream;
> +	}
> +	return decode_opcode(env, decode);
> +}
> +
>   void init_decoder(void)
>   {
>       int i;
> diff --git a/target/i386/emulate/x86_decode.h b/target/i386/emulate/x86_decode.h
> index 87cc728598..9bc7d6cc49 100644
> --- a/target/i386/emulate/x86_decode.h
> +++ b/target/i386/emulate/x86_decode.h
> @@ -269,6 +269,11 @@ typedef struct x86_decode_op {
>       target_ulong ptr;
>   } x86_decode_op;
>   
> +typedef struct x86_insn_stream {
> +	const uint8_t *bytes;
> +	size_t len;
> +} x86_insn_stream;
> +
>   typedef struct x86_decode {
>       int len;
>       uint8_t opcode[4];
> @@ -295,12 +300,18 @@ typedef struct x86_decode {
>       struct x86_modrm modrm;
>       struct x86_decode_op op[4];
>       bool is_fpu;
> +
> +	x86_insn_stream *stream;
>   } x86_decode;
>   
>   uint64_t sign(uint64_t val, int size);
>   
>   uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode);
>   
> +uint32_t decode_instruction_stream(CPUX86State *env,
> +								   struct x86_decode *decode,
> +		                           struct x86_insn_stream *stream);
> +
>   target_ulong get_reg_ref(CPUX86State *env, int reg, int rex_present,
>                            int is_extended, int size);
>   target_ulong get_reg_val(CPUX86State *env, int reg, int rex_present,
> diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c
> index 7773b51b95..73c9eb41d1 100644
> --- a/target/i386/emulate/x86_emu.c
> +++ b/target/i386/emulate/x86_emu.c
> @@ -1241,7 +1241,8 @@ static void init_cmd_handler(void)
>   bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
>   {
>       if (!_cmd_handler[ins->cmd].handler) {
> -        printf("Unimplemented handler (" TARGET_FMT_lx ") for %d (%x %x) \n", env->eip,
> +        printf("Unimplemented handler (" TARGET_FMT_lx ") for %d (%x %x) \n",
> +                env->eip,
>                   ins->cmd, ins->opcode[0],
>                   ins->opcode_len > 1 ? ins->opcode[1] : 0);
>           env->eip += ins->len;
> diff --git a/target/i386/emulate/x86_emu.h b/target/i386/emulate/x86_emu.h
> index 555b567e2c..761e83fd6b 100644
> --- a/target/i386/emulate/x86_emu.h
> +++ b/target/i386/emulate/x86_emu.h
> @@ -24,6 +24,7 @@
>   #include "cpu.h"
>   
>   struct x86_emul_ops {
> +    void (*fetch_instruction)(CPUState *cpu, void *data, target_ulong addr, int bytes);
>       void (*read_mem)(CPUState *cpu, void *data, target_ulong addr, int bytes);
>       void (*write_mem)(CPUState *cpu, void *data, target_ulong addr, int bytes);
>       void (*read_segment_descriptor)(CPUState *cpu, struct x86_segment_descriptor *desc,



  reply	other threads:[~2025-05-20 12:42 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-20 11:29 [RFC PATCH 00/25] Implementing a MSHV (Microsoft Hypervisor) accelerator Magnus Kulke
2025-05-20 11:29 ` [RFC PATCH 01/25] accel: Add Meson and config support for MSHV accelerator Magnus Kulke
2025-05-20 11:50   ` Daniel P. Berrangé
2025-05-20 14:16     ` Paolo Bonzini
2025-05-20 11:29 ` [RFC PATCH 02/25] target/i386/emulate: allow instruction decoding from stream Magnus Kulke
2025-05-20 12:42   ` Paolo Bonzini [this message]
2025-05-20 17:29   ` Wei Liu
2025-05-20 11:29 ` [RFC PATCH 03/25] target/i386/mshv: Add x86 decoder/emu implementation Magnus Kulke
2025-05-20 11:54   ` Daniel P. Berrangé
2025-05-20 13:17   ` Paolo Bonzini
2025-05-20 17:36   ` Wei Liu
2025-05-20 11:29 ` [RFC PATCH 04/25] hw/intc: Generalize APIC helper names from kvm_* to accel_* Magnus Kulke
2025-05-20 11:29 ` [RFC PATCH 05/25] include/hw/hyperv: Add MSHV ABI header definitions Magnus Kulke
2025-05-20 14:24   ` Paolo Bonzini
2025-05-20 11:29 ` [RFC PATCH 06/25] accel/mshv: Add accelerator skeleton Magnus Kulke
2025-05-20 12:02   ` Daniel P. Berrangé
2025-05-20 12:38     ` Paolo Bonzini
2025-05-20 11:30 ` [RFC PATCH 07/25] accel/mshv: Register memory region listeners Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 08/25] accel/mshv: Initialize VM partition Magnus Kulke
2025-05-20 19:07   ` Wei Liu
2025-05-22 15:42     ` Magnus Kulke
2025-05-22 17:46       ` Wei Liu
2025-05-23  8:23     ` Magnus Kulke
2025-05-23 15:37       ` Wei Liu
2025-05-23 16:13         ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 09/25] accel/mshv: Register guest memory regions with hypervisor Magnus Kulke
2025-05-20 20:07   ` Wei Liu
2025-05-23 14:17     ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 10/25] accel/mshv: Add ioeventfd support Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 11/25] accel/mshv: Add basic interrupt injection support Magnus Kulke
2025-05-20 14:18   ` Paolo Bonzini
2025-05-20 20:15   ` Wei Liu
2025-05-27 16:27     ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 12/25] accel/mshv: Add vCPU creation and execution loop Magnus Kulke
2025-05-20 13:50   ` Paolo Bonzini
2025-05-20 13:54     ` Paolo Bonzini
2025-05-23 17:05       ` Wei Liu
2025-06-06 23:06     ` Nuno Das Neves
2025-05-20 11:30 ` [RFC PATCH 13/25] accel/mshv: Add vCPU signal handling Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 14/25] target/i386/mshv: Add CPU create and remove logic Magnus Kulke
2025-05-20 21:50   ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 15/25] target/i386/mshv: Implement mshv_store_regs() Magnus Kulke
2025-05-20 22:07   ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 16/25] target/i386/mshv: Implement mshv_get_standard_regs() Magnus Kulke
2025-05-20 22:09   ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 17/25] target/i386/mshv: Implement mshv_get_special_regs() Magnus Kulke
2025-05-20 14:05   ` Paolo Bonzini
2025-05-20 22:15   ` Wei Liu
2025-05-28 13:55     ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 18/25] target/i386/mshv: Implement mshv_arch_put_registers() Magnus Kulke
2025-05-20 14:33   ` Paolo Bonzini
2025-05-20 22:22   ` Wei Liu
2025-05-28 14:30     ` Magnus Kulke
2025-06-06 19:16       ` Wei Liu
2025-06-06 19:11   ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 19/25] target/i386/mshv: Set local interrupt controller state Magnus Kulke
2025-05-20 14:03   ` Paolo Bonzini
2025-05-20 11:30 ` [RFC PATCH 20/25] target/i386/mshv: Register CPUID entries with MSHV Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 21/25] target/i386/mshv: Register MSRs " Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 22/25] target/i386/mshv: Integrate x86 instruction decoder/emulator Magnus Kulke
2025-05-20 22:38   ` Wei Liu
2025-05-28 15:10     ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 23/25] target/i386/mshv: Write MSRs to the hypervisor Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 24/25] target/i386/mshv: Implement mshv_vcpu_run() Magnus Kulke
2025-05-20 13:21   ` Paolo Bonzini
2025-05-20 22:52   ` Wei Liu
2025-06-03 15:40     ` Magnus Kulke
2025-07-01  8:35     ` Magnus Kulke
2025-07-01 15:11       ` Wei Liu
2025-07-01 15:45         ` Magnus Kulke
2025-07-01 15:47           ` Wei Liu
2025-07-01 15:51             ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 25/25] accel/mshv: Add memory remapping workaround Magnus Kulke
2025-05-20 13:53   ` Paolo Bonzini
2025-05-22 12:51     ` Magnus Kulke
2025-05-20 14:25 ` [RFC PATCH 00/25] Implementing a MSHV (Microsoft Hypervisor) accelerator Paolo Bonzini

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