From: Richard Henderson <richard.henderson@linaro.org>
To: Jonathan Behrens <jonathan@fintelia.io>, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@sifive.com>,
qemu-riscv@nongnu.org, Jonathan Behrens <fintelia@gmail.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
Date: Wed, 8 May 2019 10:47:53 -0700 [thread overview]
Message-ID: <c8e5df4d-f149-2f6a-8045-be2bf4de6e04@linaro.org> (raw)
In-Reply-To: <20190508173835.14528-1-jonathan@fintelia.io>
On 5/8/19 10:38 AM, Jonathan Behrens wrote:
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> ---
> target/riscv/csr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2019-05-08 17:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-08 17:38 [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Jonathan Behrens
2019-05-08 17:47 ` Richard Henderson [this message]
2019-05-08 20:17 ` Alistair Francis
2019-05-08 20:42 ` Palmer Dabbelt
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