* [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
@ 2019-05-08 17:38 Jonathan Behrens
2019-05-08 17:47 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jonathan Behrens @ 2019-05-08 17:38 UTC (permalink / raw)
To: qemu-devel
Cc: Jonathan Behrens, Palmer Dabbelt, qemu-riscv, Jonathan Behrens,
Sagar Karandikar
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
2019-05-08 17:38 [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Jonathan Behrens
@ 2019-05-08 17:47 ` Richard Henderson
2019-05-08 20:17 ` Alistair Francis
2019-05-08 20:42 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2019-05-08 17:47 UTC (permalink / raw)
To: Jonathan Behrens, qemu-devel
Cc: Palmer Dabbelt, qemu-riscv, Jonathan Behrens, Sagar Karandikar
On 5/8/19 10:38 AM, Jonathan Behrens wrote:
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> ---
> target/riscv/csr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
2019-05-08 17:38 [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Jonathan Behrens
2019-05-08 17:47 ` Richard Henderson
@ 2019-05-08 20:17 ` Alistair Francis
2019-05-08 20:42 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2019-05-08 20:17 UTC (permalink / raw)
To: Jonathan Behrens
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Sagar Karandikar,
Jonathan Behrens
On Wed, May 8, 2019 at 10:39 AM Jonathan Behrens <jonathan@fintelia.io> wrote:
>
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6083c782a1..1ec1222da1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
> if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> return -1;
> } else {
> - tlb_flush(CPU(riscv_env_get_cpu(env)));
> + if((val ^ env->satp) & SATP_ASID) {
> + tlb_flush(CPU(riscv_env_get_cpu(env)));
> + }
> env->satp = val;
> }
> }
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
2019-05-08 17:38 [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Jonathan Behrens
2019-05-08 17:47 ` Richard Henderson
2019-05-08 20:17 ` Alistair Francis
@ 2019-05-08 20:42 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2019-05-08 20:42 UTC (permalink / raw)
To: jonathan; +Cc: jonathan, qemu-riscv, qemu-devel, sagark, fintelia
On Wed, 08 May 2019 10:38:35 PDT (-0700), jonathan@fintelia.io wrote:
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
>
> Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
> ---
> target/riscv/csr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6083c782a1..1ec1222da1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
> if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
> return -1;
> } else {
> - tlb_flush(CPU(riscv_env_get_cpu(env)));
> + if((val ^ env->satp) & SATP_ASID) {
> + tlb_flush(CPU(riscv_env_get_cpu(env)));
> + }
> env->satp = val;
> }
> }
Thanks! I've taken this into my for-master branch, pending some testing I'll
send it up.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-05-08 17:38 [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Jonathan Behrens
2019-05-08 17:47 ` Richard Henderson
2019-05-08 20:17 ` Alistair Francis
2019-05-08 20:42 ` Palmer Dabbelt
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