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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Fan Ni <fan.ni@samsung.com>
Subject: [PULL 48/63] hw/cxl/mbox: Generalize the CCI command processing
Date: Tue, 7 Nov 2023 05:13:01 -0500	[thread overview]
Message-ID: <c9460561edbd8b2d4adbf1f7c5cb4ad4d210de4c.1699351720.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1699351720.git.mst@redhat.com>

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

By moving the parts of the mailbox command handling that are CCI type
specific out to the caller, make the main handling code generic. Rename it
to cxl_process_cci_message() to reflect this new generality.

Change the type3 mailbox handling (reused shortly for the switch
mailbox CCI) to take a snapshot of the mailbox input data rather
than operating on it in place.  This reduces the chance of bugs
due to aliasing going forwars.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Message-Id: <20231023160806.13206-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/cxl/cxl_device.h |  5 +++-
 hw/cxl/cxl-device-utils.c   | 44 +++++++++++++++++++++++++++++++-
 hw/cxl/cxl-mailbox-utils.c  | 51 ++++++++-----------------------------
 3 files changed, 57 insertions(+), 43 deletions(-)

diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 779ca85319..6f8040b5ff 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -260,7 +260,10 @@ CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
 
 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
-void cxl_process_mailbox(CXLCCI *cci);
+int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
+                            size_t len_in, uint8_t *pl_in,
+                            size_t *len_out, uint8_t *pl_out,
+                            bool *bg_started);
 
 #define cxl_device_cap_init(dstate, reg, cap_id, ver)                      \
     do {                                                                   \
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index 327949a805..eb86634250 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -157,7 +157,49 @@ static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
 
     if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
                          DOORBELL)) {
-        cxl_process_mailbox(cci);
+        uint64_t command_reg =
+            cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
+        uint8_t cmd_set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD,
+                                     COMMAND_SET);
+        uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
+        size_t len_in = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
+        uint8_t *pl = cxl_dstate->mbox_reg_state + A_CXL_DEV_CMD_PAYLOAD;
+        /*
+         * Copy taken to avoid need for individual command handlers to care
+         * about aliasing.
+         */
+        g_autofree uint8_t *pl_in_copy = NULL;
+        size_t len_out = 0;
+        uint64_t status_reg;
+        bool bg_started = false;
+        int rc;
+
+        pl_in_copy = g_memdup2(pl, len_in);
+        if (len_in == 0 || pl_in_copy) {
+            /* Avoid stale data  - including from earlier cmds */
+            memset(pl, 0, CXL_MAILBOX_MAX_PAYLOAD_SIZE);
+            rc = cxl_process_cci_message(cci, cmd_set, cmd, len_in, pl_in_copy,
+                                         &len_out, pl, &bg_started);
+        } else {
+            rc = CXL_MBOX_INTERNAL_ERROR;
+        }
+
+        /* Set bg and the return code */
+        status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, BG_OP,
+                                bg_started ? 1 : 0);
+        status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, ERRNO, rc);
+        /* Set the return length */
+        command_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_CMD, COMMAND_SET, cmd_set);
+        command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD,
+                                 COMMAND, cmd);
+        command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD,
+                                 LENGTH, len_out);
+
+        cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
+        cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
+        /* Tell the host we're done */
+        ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
+                         DOORBELL, 0);
     }
 }
 
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 5484dfbbf1..239acc659d 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -754,58 +754,27 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = {
         cmd_media_clear_poison, 72, 0 },
 };
 
-void cxl_process_mailbox(CXLCCI *cci)
+int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
+                            size_t len_in, uint8_t *pl_in, size_t *len_out,
+                            uint8_t *pl_out, bool *bg_started)
 {
-    uint16_t ret = CXL_MBOX_SUCCESS;
     const struct cxl_cmd *cxl_cmd;
-    uint64_t status_reg = 0;
     opcode_handler h;
-    CXLDeviceState *cxl_dstate = &CXL_TYPE3(cci->d)->cxl_dstate;
-    uint64_t command_reg = cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
 
-    uint8_t set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET);
-    uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
-    uint16_t len_in = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
-    uint8_t *pl = cxl_dstate->mbox_reg_state + A_CXL_DEV_CMD_PAYLOAD;
-    /*
-     * Copy taken to avoid need for individual command handlers to care
-     * about aliasing.
-     */
-    g_autofree uint8_t *pl_in_copy = NULL;
-    size_t len_out = 0;
-
-    pl_in_copy = g_memdup2(pl, len_in);
-    /* Avoid stale data - including from earlier commands */
-    memset(pl, 0, CXL_MAILBOX_MAX_PAYLOAD_SIZE);
+    *len_out = 0;
     cxl_cmd = &cci->cxl_cmd_set[set][cmd];
     h = cxl_cmd->handler;
-    if (h) {
-        if (len_in == cxl_cmd->in || cxl_cmd->in == ~0) {
-            ret = (*h)(cxl_cmd, pl, len_in, pl, &len_out, cci);
-            assert(len_out <= cci->payload_max);
-        } else {
-            ret = CXL_MBOX_INVALID_PAYLOAD_LENGTH;
-        }
-    } else {
+    if (!h) {
         qemu_log_mask(LOG_UNIMP, "Command %04xh not implemented\n",
                       set << 8 | cmd);
-        ret = CXL_MBOX_UNSUPPORTED;
+        return CXL_MBOX_UNSUPPORTED;
     }
 
-    /* Set the return code */
-    status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, ERRNO, ret);
+    if (len_in != cxl_cmd->in && cxl_cmd->in != ~0) {
+        return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
+    }
 
-    /* Set the return length */
-    command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND_SET, 0);
-    command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND, 0);
-    command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH, len_out);
-
-    cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
-    cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
-
-    /* Tell the host we're done */
-    ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
-                     DOORBELL, 0);
+    return (*h)(cxl_cmd, pl_in, len_in, pl_out, len_out, cci);
 }
 
 void cxl_init_cci(CXLCCI *cci, size_t payload_max)
-- 
MST



  parent reply	other threads:[~2023-11-07 10:22 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-07 10:09 [PULL 00/63] virtio,pc,pci: features, fixes Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 01/63] vhost-user.rst: Improve [GS]ET_VRING_BASE doc Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 02/63] vhost-user.rst: Clarify enabling/disabling vrings Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 03/63] vhost-user.rst: Introduce suspended state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 04/63] vhost-user.rst: Migrating back-end-internal state Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 05/63] vhost-user: Interface for migration state transfer Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 06/63] vhost: Add high-level state save/load functions Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 07/63] vhost-user-fs: Implement internal migration Michael S. Tsirkin
2023-11-07 10:09 ` [PULL 08/63] Add virtio-sound device stub Michael S. Tsirkin
2023-11-09 14:30   ` Peter Maydell
2023-11-09 15:50     ` Manos Pitsidianakis
2023-11-09 16:06       ` Peter Maydell
2023-11-09 16:10       ` Alex Bennée
2023-11-07 10:10 ` [PULL 09/63] Add virtio-sound-pci device Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 10/63] virtio-sound: handle control messages and streams Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 11/63] virtio-sound: handle VIRTIO_SND_R_PCM_INFO request Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 12/63] virtio-sound: handle VIRTIO_SND_R_PCM_{START,STOP} Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 13/63] virtio-sound: handle VIRTIO_SND_R_PCM_SET_PARAMS Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 14/63] virtio-sound: handle VIRTIO_SND_R_PCM_PREPARE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 15/63] virtio-sound: handle VIRTIO_SND_R_PCM_RELEASE Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 16/63] virtio-sound: implement audio output (TX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 17/63] virtio-sound: implement audio capture (RX) Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 18/63] docs/system: add basic virtio-snd documentation Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 19/63] vdpa: Restore hash calculation state Michael S. Tsirkin
2023-11-07 10:10 ` [PULL 20/63] vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 21/63] vdpa: Add SetSteeringEBPF method for NetClientState Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 22/63] vdpa: Restore receive-side scaling state Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 23/63] vdpa: Allow VIRTIO_NET_F_RSS in SVQ Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 24/63] tests: test-smp-parse: Add the test for cores/threads per socket helpers Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 25/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 26/63] tests: bios-tables-test: Add test for smbios type4 count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 27/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 28/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core " Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 29/63] tests: bios-tables-test: Add test for smbios type4 core count Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 30/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 31/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 32/63] tests: bios-tables-test: Extend smbios core count2 test to cover general topology Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 33/63] tests: bios-tables-test: Update ACPI table binaries for smbios core count2 test Michael S. Tsirkin
2023-11-07 10:11 ` [PULL 34/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 35/63] tests: bios-tables-test: Add test for smbios type4 thread count Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 36/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 37/63] tests: bios-tables-test: Prepare the ACPI table change for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 38/63] tests: bios-tables-test: Add test for smbios type4 thread count2 Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 39/63] tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 40/63] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 41/63] hw/cxl: Use switch statements for read and write of cachemem registers Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 42/63] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 43/63] hw/cxl: Line length reductions Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 44/63] hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 45/63] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 46/63] hw/cxl/mbox: Split mailbox command payload into separate input and output Michael S. Tsirkin
2023-11-07 10:12 ` [PULL 47/63] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Michael S. Tsirkin
2023-11-07 10:13 ` Michael S. Tsirkin [this message]
2023-11-07 10:13 ` [PULL 49/63] hw/pci-bridge/cxl_upstream: Move defintion of device to header Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 50/63] hw/cxl: Add a switch mailbox CCI function Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 51/63] hw/cxl/mbox: Add Information and Status / Identify command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 52/63] hw/cxl/mbox: Add Physical Switch " Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 53/63] hw/pci-bridge/cxl_downstream: Set default link width and link speed Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 54/63] hw/cxl: Implement Physical Ports status retrieval Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 55/63] hw/cxl/mbox: Add support for background operations Michael S. Tsirkin
2023-11-09 14:44   ` Peter Maydell
2023-11-10  4:25     ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 56/63] hw/cxl/mbox: Wire up interrupts for background completion Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 57/63] hw/cxl: Add support for device sanitation Michael S. Tsirkin
2023-11-09 14:39   ` Peter Maydell
2023-11-10  4:14     ` Davidlohr Bueso
2023-11-07 10:13 ` [PULL 58/63] hw/cxl/mbox: Add Get Background Operation Status Command Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 59/63] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 60/63] hw/cxl: Add dummy security state get Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 61/63] hw/cxl: Add tunneled command support to mailbox for switch cci Michael S. Tsirkin
2023-11-07 10:13 ` [PULL 62/63] acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point Michael S. Tsirkin
2023-11-07 10:14 ` [PULL 63/63] acpi/tests/avocado/bits: enable console logging from bits VM Michael S. Tsirkin
2023-11-07 13:40 ` [PULL 00/63] virtio,pc,pci: features, fixes Stefan Hajnoczi

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