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* [PULL 0/5] riscv-to-apply queue
@ 2024-08-06  6:25 Alistair Francis
  2024-08-06  6:25 ` [PULL 1/5] target/riscv: Remove redundant insn length check for zama16b Alistair Francis
                   ` (5 more replies)
  0 siblings, 6 replies; 11+ messages in thread
From: Alistair Francis @ 2024-08-06  6:25 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit e7207a9971dd41618b407030902b0b2256deb664:

  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-08-06 08:02:34 +1000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240806-2

for you to fetch changes up to b3a34eb90d8264bd73ccb25295b1a7e271a9029c:

  roms/opensbi: Update to v1.5.1 (2024-08-06 15:01:01 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* roms/opensbi: update to v1.5.1
* target/riscv: Add asserts for out-of-bound access
* Remove redundant insn length check for zama16b

----------------------------------------------------------------
Atish Patra (1):
      target/riscv: Add asserts for out-of-bound access

Daniel Henrique Barboza (1):
      roms/opensbi: Update to v1.5.1

LIU Zhiwei (3):
      target/riscv: Remove redundant insn length check for zama16b
      target/riscv: Add MXLEN check for F/D/Q applies to zama16b
      target/riscv: Relax fld alignment requirement

 target/riscv/pmu.c                             |   4 ++++
 target/riscv/insn_trans/trans_rvd.c.inc        |  18 ++++++++++++++++--
 target/riscv/insn_trans/trans_rvf.c.inc        |   4 ++--
 target/riscv/insn_trans/trans_rvi.c.inc        |   4 ++--
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 268312 -> 268312 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 272504 -> 272504 bytes
 roms/opensbi                                   |   2 +-
 7 files changed, 25 insertions(+), 7 deletions(-)


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PULL 0/5] riscv-to-apply queue
@ 2023-07-19  4:45 Alistair Francis
  2023-07-19 19:30 ` Peter Maydell
  0 siblings, 1 reply; 11+ messages in thread
From: Alistair Francis @ 2023-07-19  4:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7:

  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1

for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179:

  target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 8.1

* Fix LMUL check to use VLEN
* Fix typo field in NUMA error_report
* check priv_ver before auto-enable zca/zcd/zcf
* Fix disas output of upper immediates
* tidy CPU firmware section

----------------------------------------------------------------
Christoph Müllner (1):
      riscv/disas: Fix disas output of upper immediates

Daniel Henrique Barboza (2):
      docs/system/target-riscv.rst: tidy CPU firmware section
      target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

Rob Bradford (1):
      target/riscv: Fix LMUL check to use VLEN

Zhao Liu (1):
      hw/riscv: Fix typo field in error_report

 docs/system/target-riscv.rst | 24 ++++++++++++++++--------
 disas/riscv.h                |  2 ++
 disas/riscv.c                | 19 ++++++++++++++++---
 hw/riscv/numa.c              |  4 ++--
 target/riscv/cpu.c           |  3 ++-
 target/riscv/vector_helper.c |  4 ++--
 6 files changed, 40 insertions(+), 16 deletions(-)


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PULL 0/5] riscv-to-apply queue
@ 2020-07-22 16:48 Alistair Francis
  2020-07-24  9:51 ` Peter Maydell
  0 siblings, 1 reply; 11+ messages in thread
From: Alistair Francis @ 2020-07-22 16:48 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alistair Francis

The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1

for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d:

  target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700)

----------------------------------------------------------------
This PR contains a few RISC-V fixes.

The main fix is the correction of the goldfish RTC time. On top of that
some small fixes to the recently added vector extensions have been added
(including an assert that fixed a coverity report). There is a change in
the SiFive E debug memory size to match hardware. Finally there is a fix
for PMP accesses.

----------------------------------------------------------------
Bin Meng (1):
      hw/riscv: sifive_e: Correct debug block size

Jessica Clarke (1):
      goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH

LIU Zhiwei (2):
      target/riscv: Quiet Coverity complains about vamo*
      target/riscv: fix vector index load/store constraints

Zong Li (1):
      target/riscv: Fix the range of pmpcfg of CSR funcion table

 include/hw/rtc/goldfish_rtc.h           |  1 +
 hw/riscv/sifive_e.c                     |  2 +-
 hw/rtc/goldfish_rtc.c                   | 17 ++++++++++++++---
 target/riscv/csr.c                      |  2 +-
 target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++++-
 5 files changed, 27 insertions(+), 6 deletions(-)


^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-08-06  9:43 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-06  6:25 [PULL 0/5] riscv-to-apply queue Alistair Francis
2024-08-06  6:25 ` [PULL 1/5] target/riscv: Remove redundant insn length check for zama16b Alistair Francis
2024-08-06  6:25 ` [PULL 2/5] target/riscv: Add MXLEN check for F/D/Q applies to zama16b Alistair Francis
2024-08-06  6:25 ` [PULL 3/5] target/riscv: Relax fld alignment requirement Alistair Francis
2024-08-06  6:25 ` [PULL 4/5] target/riscv: Add asserts for out-of-bound access Alistair Francis
2024-08-06  6:25 ` [PULL 5/5] roms/opensbi: Update to v1.5.1 Alistair Francis
2024-08-06  9:42 ` [PULL 0/5] riscv-to-apply queue Richard Henderson
  -- strict thread matches above, loose matches on Subject: below --
2023-07-19  4:45 Alistair Francis
2023-07-19 19:30 ` Peter Maydell
2020-07-22 16:48 Alistair Francis
2020-07-24  9:51 ` Peter Maydell

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