* [PATCH 0/2] Added the ability to delegate LCOFI to VS
@ 2023-12-21 11:36 Vadim Shakirov
2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Vadim Shakirov @ 2023-12-21 11:36 UTC (permalink / raw)
To: qemu-devel
Cc: Vadim Shakirov, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv
This series of patches adds LCOFI delegation from HS-mode to VS-mode.
This possibility must be implemented, as in the AIA spec in section 6.3.2
it is indicated in table 6.1 that in the case when the hideleg bit is set,
the corresponding vsip bit is an alias to the corresponding sip bit, also
for enable registers.
Vadim Shakirov (2):
target/riscv/csr: Rename groups of interrupts
target/riscv/csr: Added the ability to delegate LCOFI to VS
target/riscv/csr.c | 50 ++++++++++++++++++++++++++++++----------------
1 file changed, 33 insertions(+), 17 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/2] target/riscv/csr: Rename groups of interrupts 2023-12-21 11:36 [PATCH 0/2] Added the ability to delegate LCOFI to VS Vadim Shakirov @ 2023-12-21 11:36 ` Vadim Shakirov 2023-12-21 16:03 ` Daniel Henrique Barboza 2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Vadim Shakirov 2024-01-04 3:54 ` [PATCH 0/2] " Alistair Francis 2 siblings, 1 reply; 7+ messages in thread From: Vadim Shakirov @ 2023-12-21 11:36 UTC (permalink / raw) To: qemu-devel Cc: Vadim Shakirov, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv In AIA spec in 5.1 chapter says that "... the AIA categorizes the counter overflow interrupt (code 13) as a local interrupt. It is assumed furthermore that any future definitions for reserved interrupt numbers 14 and 15 will also be local interrupts" and than LCOFI belongs to LOCAL_INTERRUPTS Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> --- target/riscv/csr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d69bff5a67..36f807d5f6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1120,18 +1120,18 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, /* Machine constants */ #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ - MIP_LCOFIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) +#define LOCAL_INTERRUPTS ((uint64_t)(MIP_LCOFIP)) #define VSTOPI_NUM_SRCS 5 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - HS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -1163,7 +1163,7 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | - SIP_LCOFIP; + LOCAL_INTERRUPTS; static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; @@ -2471,7 +2471,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; + uint64_t mask = env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { @@ -2693,7 +2693,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno, } if (ret_val) { - *ret_val &= env->mideleg & S_MODE_INTERRUPTS; + *ret_val &= env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); } return ret; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv/csr: Rename groups of interrupts 2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov @ 2023-12-21 16:03 ` Daniel Henrique Barboza 0 siblings, 0 replies; 7+ messages in thread From: Daniel Henrique Barboza @ 2023-12-21 16:03 UTC (permalink / raw) To: Vadim Shakirov, qemu-devel Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, qemu-riscv On 12/21/23 08:36, Vadim Shakirov wrote: > In AIA spec in 5.1 chapter says that "... the AIA categorizes the counter > overflow interrupt (code 13) as a local interrupt. It is assumed furthermore > that any future definitions for reserved interrupt numbers 14 and 15 will > also be local interrupts" and than LCOFI belongs to LOCAL_INTERRUPTS > > Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/csr.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d69bff5a67..36f807d5f6 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1120,18 +1120,18 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > /* Machine constants */ > > #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) > -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ > - MIP_LCOFIP)) > +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) > #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) > #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) > +#define LOCAL_INTERRUPTS ((uint64_t)(MIP_LCOFIP)) > > #define VSTOPI_NUM_SRCS 5 > > static const uint64_t delegable_ints = S_MODE_INTERRUPTS | > - VS_MODE_INTERRUPTS; > + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; > static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > - HS_MODE_INTERRUPTS; > + HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ > (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ > @@ -1163,7 +1163,7 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | > SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | > SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; > static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | > - SIP_LCOFIP; > + LOCAL_INTERRUPTS; > static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP; > @@ -2471,7 +2471,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; > + uint64_t mask = env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); > > if (env->virt_enabled) { > if (env->hvictl & HVICTL_VTI) { > @@ -2693,7 +2693,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno, > } > > if (ret_val) { > - *ret_val &= env->mideleg & S_MODE_INTERRUPTS; > + *ret_val &= env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); > } > > return ret; ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS 2023-12-21 11:36 [PATCH 0/2] Added the ability to delegate LCOFI to VS Vadim Shakirov 2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov @ 2023-12-21 11:36 ` Vadim Shakirov 2023-12-21 16:03 ` Daniel Henrique Barboza 2024-01-04 3:54 ` [PATCH 0/2] " Alistair Francis 2 siblings, 1 reply; 7+ messages in thread From: Vadim Shakirov @ 2023-12-21 11:36 UTC (permalink / raw) To: qemu-devel Cc: Vadim Shakirov, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv In the AIA specification in the paragraph "Virtual interrupts for VS level" it is indicated for interrupts 13-63: if the bit in hideleg is enabled, then the corresponding vsip and vsie bits are aliases to sip and sie Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> --- target/riscv/csr.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 36f807d5f6..46a5d0c69a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1129,7 +1129,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, static const uint64_t delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; -static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ @@ -1167,7 +1167,7 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; -static const target_ulong vsip_writable_mask = MIP_VSSIP; +static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, @@ -2416,20 +2416,34 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, return write_mstatus(env, CSR_MSTATUS, newval); } + +static uint64_t vsi_to_mi(uint64_t vsi) +{ + uint64_t mi; + + mi = (vsi & (VS_MODE_INTERRUPTS >> 1)) << 1; + mi |= vsi & LOCAL_INTERRUPTS; + + return mi; +} + static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); /* Bring VS-level bits to correct position */ - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val = vsi_to_mi(new_val); + wr_mask = vsi_to_mi(wr_mask); ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); + if (ret_val) { - *ret_val = (rval & mask) >> 1; + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); } return ret; @@ -2630,16 +2644,18 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); /* Bring VS-level bits to correct position */ - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val = vsi_to_mi(new_val); + wr_mask = vsi_to_mi(wr_mask); ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask & vsip_writable_mask); if (ret_val) { - *ret_val = (rval & mask) >> 1; + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); } return ret; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS 2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Vadim Shakirov @ 2023-12-21 16:03 ` Daniel Henrique Barboza 0 siblings, 0 replies; 7+ messages in thread From: Daniel Henrique Barboza @ 2023-12-21 16:03 UTC (permalink / raw) To: Vadim Shakirov, qemu-devel Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, qemu-riscv On 12/21/23 08:36, Vadim Shakirov wrote: > In the AIA specification in the paragraph "Virtual interrupts for VS level" > it is indicated for interrupts 13-63: if the bit in hideleg is enabled, > then the corresponding vsip and vsie bits are aliases to sip and sie > > Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/csr.c | 36 ++++++++++++++++++++++++++---------- > 1 file changed, 26 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 36f807d5f6..46a5d0c69a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1129,7 +1129,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > > static const uint64_t delegable_ints = S_MODE_INTERRUPTS | > VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > -static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; > +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > @@ -1167,7 +1167,7 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | > static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP; > -static const target_ulong vsip_writable_mask = MIP_VSSIP; > +static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; > > const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > @@ -2416,20 +2416,34 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, > return write_mstatus(env, CSR_MSTATUS, newval); > } > > + > +static uint64_t vsi_to_mi(uint64_t vsi) > +{ > + uint64_t mi; > + > + mi = (vsi & (VS_MODE_INTERRUPTS >> 1)) << 1; > + mi |= vsi & LOCAL_INTERRUPTS; > + > + return mi; > +} > + > static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, > uint64_t *ret_val, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | > + LOCAL_INTERRUPTS); > > /* Bring VS-level bits to correct position */ > - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > + new_val = vsi_to_mi(new_val); > + wr_mask = vsi_to_mi(wr_mask); > > ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); > + > if (ret_val) { > - *ret_val = (rval & mask) >> 1; > + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; > + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); > } > > return ret; > @@ -2630,16 +2644,18 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | > + LOCAL_INTERRUPTS); > > /* Bring VS-level bits to correct position */ > - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > + new_val = vsi_to_mi(new_val); > + wr_mask = vsi_to_mi(wr_mask); > > ret = rmw_mip64(env, csrno, &rval, new_val, > wr_mask & mask & vsip_writable_mask); > if (ret_val) { > - *ret_val = (rval & mask) >> 1; > + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; > + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); > } > > return ret; ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/2] Added the ability to delegate LCOFI to VS 2023-12-21 11:36 [PATCH 0/2] Added the ability to delegate LCOFI to VS Vadim Shakirov 2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov 2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Vadim Shakirov @ 2024-01-04 3:54 ` Alistair Francis 2024-01-15 9:59 ` Vadim Shakirov 2 siblings, 1 reply; 7+ messages in thread From: Alistair Francis @ 2024-01-04 3:54 UTC (permalink / raw) To: Vadim Shakirov Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv On Fri, Dec 22, 2023 at 1:08 AM Vadim Shakirov <vadim.shakirov@syntacore.com> wrote: > > This series of patches adds LCOFI delegation from HS-mode to VS-mode. > > This possibility must be implemented, as in the AIA spec in section 6.3.2 > it is indicated in table 6.1 that in the case when the hideleg bit is set, > the corresponding vsip bit is an alias to the corresponding sip bit, also > for enable registers. > > Vadim Shakirov (2): > target/riscv/csr: Rename groups of interrupts > target/riscv/csr: Added the ability to delegate LCOFI to VS Thanks for the patch. Do you mind rebasing this on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a new version? Alistair > > target/riscv/csr.c | 50 ++++++++++++++++++++++++++++++---------------- > 1 file changed, 33 insertions(+), 17 deletions(-) > > -- > 2.34.1 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/2] Added the ability to delegate LCOFI to VS 2024-01-04 3:54 ` [PATCH 0/2] " Alistair Francis @ 2024-01-15 9:59 ` Vadim Shakirov 0 siblings, 0 replies; 7+ messages in thread From: Vadim Shakirov @ 2024-01-15 9:59 UTC (permalink / raw) To: Alistair Francis Cc: qemu-devel@nongnu.org, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv@nongnu.org [-- Attachment #1: Type: text/plain, Size: 1477 bytes --] This functionality turns out to have already been added by commit 40336d5b1d4c6b8b8b38c77fda254457d44fe90b Vadim ________________________________ От: Alistair Francis <alistair23@gmail.com> Отправлено: 4 января 2024 г. 6:54:27 Кому: Vadim Shakirov Копия: qemu-devel@nongnu.org; Palmer Dabbelt; Alistair Francis; Bin Meng; Weiwei Li; Daniel Henrique Barboza; Liu Zhiwei; qemu-riscv@nongnu.org Тема: Re: [PATCH 0/2] Added the ability to delegate LCOFI to VS «Внимание! Данное письмо от внешнего адресата!» On Fri, Dec 22, 2023 at 1:08 AM Vadim Shakirov <vadim.shakirov@syntacore.com> wrote: > > This series of patches adds LCOFI delegation from HS-mode to VS-mode. > > This possibility must be implemented, as in the AIA spec in section 6.3.2 > it is indicated in table 6.1 that in the case when the hideleg bit is set, > the corresponding vsip bit is an alias to the corresponding sip bit, also > for enable registers. > > Vadim Shakirov (2): > target/riscv/csr: Rename groups of interrupts > target/riscv/csr: Added the ability to delegate LCOFI to VS Thanks for the patch. Do you mind rebasing this on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a new version? Alistair > > target/riscv/csr.c | 50 ++++++++++++++++++++++++++++++---------------- > 1 file changed, 33 insertions(+), 17 deletions(-) > > -- > 2.34.1 > > [-- Attachment #2: Type: text/html, Size: 3067 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-01-15 9:59 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-21 11:36 [PATCH 0/2] Added the ability to delegate LCOFI to VS Vadim Shakirov 2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov 2023-12-21 16:03 ` Daniel Henrique Barboza 2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Vadim Shakirov 2023-12-21 16:03 ` Daniel Henrique Barboza 2024-01-04 3:54 ` [PATCH 0/2] " Alistair Francis 2024-01-15 9:59 ` Vadim Shakirov
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