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From: Gustavo Romero <gustavo.romero@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: Re: [PATCH v2 1/6] linux-user/aarch64: Extend PR_SET_TAGGED_ADDR_CTRL for FEAT_MTE3
Date: Tue, 6 Feb 2024 12:18:07 -0300	[thread overview]
Message-ID: <c9b3e48e-1bcd-f3f7-0900-3148ef7a1d52@linaro.org> (raw)
In-Reply-To: <20240206030527.169147-2-richard.henderson@linaro.org>

On 2/6/24 12:05 AM, Richard Henderson wrote:
> When MTE3 is supported, the kernel maps
>    PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
> to
>    MTE_CTRL_TCF_ASYMM
> and from there to
>    SCTLR_EL1.TCF0 = 3
> 
> There is no error reported for setting ASYNC | SYNC when MTE3 is not
> supported; the kernel simply selects the ASYNC behavior of TCF0=2.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   linux-user/aarch64/target_prctl.h | 25 +++++++++++++------------
>   1 file changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
> index 5067e7d731..49bd16aa95 100644
> --- a/linux-user/aarch64/target_prctl.h
> +++ b/linux-user/aarch64/target_prctl.h
> @@ -173,21 +173,22 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
>       env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
>   
>       if (cpu_isar_feature(aa64_mte, cpu)) {
> -        switch (arg2 & PR_MTE_TCF_MASK) {
> -        case PR_MTE_TCF_NONE:
> -        case PR_MTE_TCF_SYNC:
> -        case PR_MTE_TCF_ASYNC:
> -            break;
> -        default:
> -            return -EINVAL;
> -        }
> -
>           /*
>            * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
> -         * Note that the syscall values are consistent with hw.
> +         * Note that SYNC | ASYNC -> ASYMM with FEAT_MTE3,
> +         * otherwise mte_update_sctlr_user chooses ASYNC.
>            */
> -        env->cp15.sctlr_el[1] =
> -            deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
> +        unsigned tcf = 0;
> +        if (arg2 & PR_MTE_TCF_ASYNC) {
> +            if ((arg2 & PR_MTE_TCF_SYNC) && cpu_isar_feature(aa64_mte3, cpu)) {
> +                tcf = 3;
> +            } else {
> +                tcf = 2;
> +            }
> +        } else if (arg2 & PR_MTE_TCF_SYNC) {
> +            tcf = 1;
> +        }
> +        env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
>   
>           /*
>            * Write PR_MTE_TAG to GCR_EL1[Exclude].
> 

Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>


  parent reply	other threads:[~2024-02-06 15:18 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-06  3:05 [PATCH v2 0/6] target/arm: assorted mte fixes Richard Henderson
2024-02-06  3:05 ` [PATCH v2 1/6] linux-user/aarch64: Extend PR_SET_TAGGED_ADDR_CTRL for FEAT_MTE3 Richard Henderson
2024-02-06 14:23   ` Peter Maydell
2024-02-07  0:31     ` Richard Henderson
2024-02-07  2:10     ` Richard Henderson
2024-02-06 15:18   ` Gustavo Romero [this message]
2024-02-06  3:05 ` [PATCH v2 2/6] target/arm: Fix nregs computation in do_ld_zpa Richard Henderson
2024-02-06 14:46   ` Peter Maydell
2024-02-07  0:42     ` Richard Henderson
2024-02-06  3:05 ` [PATCH v2 3/6] target/arm: Adjust and validate mtedesc sizem1 Richard Henderson
2024-02-06 14:49   ` Peter Maydell
2024-02-06  3:05 ` [PATCH v2 4/6] target/arm: Split out make_svemte_desc Richard Henderson
2024-02-06 14:52   ` Peter Maydell
2024-02-06  3:05 ` [PATCH v2 5/6] target/arm: Handle mte in do_ldrq, do_ldro Richard Henderson
2024-02-06 14:53   ` Peter Maydell
2024-02-06  3:05 ` [PATCH v2 6/6] target/arm: Fix SVE/SME gross MTE suppression checks Richard Henderson
2024-02-06 14:54   ` Peter Maydell
2024-02-06 14:54 ` [PATCH v2 0/6] target/arm: assorted mte fixes Peter Maydell
2024-02-06 20:10   ` Richard Henderson
2024-02-06 15:17 ` Gustavo Romero

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